• State TI Thinks Resolved
  • Locked Locked
  • Replies 9 replies
  • Answers 3 answers
  • Subscribers 46 subscribers
  • Views 577 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS8363: On M0, M1 and CONVST pins

Jorge Vega
Intellectual 300 points
Part Number: ADS8363
Other Parts Discussed in Thread: INA250

Hello,  could you guide me in the use of the M0, M1 and CONVST pins?

I have a differential input and three pseudo-differential inputs that I need to sample. Given this how should I configure M0, M1 and the CONVST pins?

Many thanks for your help.

-jva

  • 0
    TI__Guru 63196 points

    Hello Jorge,

    Welcome to our forum and thank you for your post!

    It looks like the PDE bit (CONFIG register, bit 6) applies to both ADC A and ADC B. This means that the multiplexer will either be configured for fully-differential mode or pseudo-differential mode for both ADC channels.

    To combine both differential and pseudo-differential signals with the ADS8363, you must configure the MUX for pseudo-differential mode. As an example, use ADC A for the differential signal and ADC B for the pseudo-differential signal. The positive end of the differential signal would be tied to the CHA[1-3] pins and the negative end would be tied to CMA. The 3 pseudo-differential inputs would be tied to CHB[1-3] and the common-mode to CMB. As you cycle through the MUX (manually or automatically), ADC A will always be measuring the same differential signal (CHAn - CMA) while ADC B will cycle through the 3 pseudo-differential signals (CHBn - CMB). The only downside I can see is that the differential signal on ADC A will be sampled 3x faster than the pseudo-differential signals, but you could also down-sample the differential signal later.

    CONVST is simply the conversion start signal used to sample both ADC channels. The use of CONVST will not depend on the input signal configuration or the M0 and M1 pins.

  • 0
    Intellectual 300 points

    Hello Ryan, thanks for your reply.  Let me reflect back ur comments.

    1. The chip gets configured by the PDE (pseudo-differential enable) bit in the CONFIG register into ALL 8 channels of pseudo-diff inputs OR 4 fully-diff inputs.

    2. To mix pseudo diff and fully-diff the PDE bit needs to be set to 1.  This sets the chip into ALL 8 channels of pseudo-diff inputs, however I can connect the the fully differential positive signal on CHA0 while the negative on CMA.

    Comment on item 2. 

    - Does this mean that CHA1, CHA2 and CHA3 will not be useful anymore?

    - You wrote " The positive end of the differential signal would be tied to the CHA[1-3] pins and the negative end would be tied to CMA."  does this mean all channels CHA[1-3] are shorted together to the positive input?

    3. CONVST is independent and just signals the start of a conversion.

    Comments on item 3.

    - What is the implication of grounding CONVST while in manual mode (M0=1, M1=0).

    Additional questions:

    1. I see the big deal about using ADS8363 like this: I can sample 2 signals simultaneously at the same time by ADCA and ADCB.  So in my application I am sampling current with channel A and voltage with channel B.  These two measurements are done at the same time for a one-to-one sampling. Is this assessment correct?

    2. Does CMA and CMB need caps to ground like the REFIOs pins 22uF?

    3. What is the significance of grounding SDI as in figure 47, page 44 of the D/S.

    Many thanks.  Appreciative of your time.

     

  • 0 in reply to Jorge Vega
    TI__Guru 63196 points

    Hello Jorge,

    1. Correct
    2. See comments for item 2:
      1. In order to measure the three pseudo-differential input signals (CHB1, CHB2, and CHB3) with respect to CMB, you will need to execute a register write and change the MUX settings accordingly. However, the MUX for channel A will change at the same time (CHA0 and CHB0 are selected, then CHA1 and CHB1, etc.). It sounds like your goal is to always measure the differential signal on Channel A, so one way to do this is to short the positive differential input to all CHAn pins and connect the negative differential input to CMA. The differential input voltage to ADC A [CHAn - CMA] will always be the same signal.
      2. Keep in mind that the differential signal will be sampled 3x faster than each pseudo-differential signal.
    3. CONVST cannot be tied to ground. It is imperative to control CONVST to begin each conversion cycle. "Manual mode" only means that the host must write to the device each time you wish to change the MUX. "Automatic mode" will change the MUX setting after each conversion automatically and repeat in the same order.
    4. CMA and CMB can be treated as normal analog inputs and do not require a large bypass cap like the REFIO pins (these pins are strictly DC inputs).
    5. SDI should not be grounded in Figure 47 as M0 = 0 (manual mode). We've noted this mistake, thanks!

    Best regards,

  • 0 in reply to Ryan Andrews
    Intellectual 300 points

    Hello Ryan,

    Thank you for your comments.  I am almost done wiring up my implementation but had a question concerning the filter that each input needs to have.  

    Equations 5 and 6 on the D/S shows how to get R and C given that a F_filter is chosen.  I want to ask you about F_filter. 

    I am using half clock mode since I am configured for pseudo differential inputs which corresponds to 500ksps.  The slowest signal into the ADC comes out of an INA250 (current shunt monitor) with a bandwidth of 50Khz.  Based on this I am inclined at selecting a filter that is 10x this frequency (2x is Nyquist, 10x incorporates plenty more) so F_filter ~ 500KHz.  Could you give me some pointers to go by on how the 500kbps would work out with a signal filtered at 500KHz (I am not sure if I have a feel for this)? Or general thoughts that may serve as pointers would be welcomed.   

    Many thanks for your help.

    Jorge  

  • 0 in reply to Jorge Vega
    TI__Guru 63196 points

    Hi Jorge,

    I think we are confusing various "bandwidths" based on your last post.

    1. @ 500 kSPS, the ADS8363 will satisfy the Nyquist criteria for signals less than 250 kHz. Given that the INA250 only supports 50 kHz and lower (see #2), you could significantly reduce the ADC sampling rate and save on power. 
    2. The INA250 has a bandwidth of 50 kHz. If you refer to Figure 16 of the INA250 data sheet, this bandwidth is where the gain of the INA begins to diminish.
    3. The RC filter at the input of the ADC is primarily a "charge-bucket" which serves to provide instantaneous current to the internal ADC sample-and-hold capacitors. The better the applied input voltage settles during sampling, the more accurate the results. If you need to implement some low-pass antialiasing filtering, it is recommended to do that before the ADC inputs and follow the filter with a wide bandwidth amplifier to drive the ADC.

    These topics and many others are covered in our TI Precision Labs - ADC online training. Furthermore, I found this ADC Cookbook circuit that looks close to what you're trying to implement. Notice that the current-shunt amplifier is followed by another signal conditioning and wide bandwidth driver stage before the ADC.

    Best regards,

  • 0 in reply to Ryan Andrews
    Intellectual 300 points

    Hi Andrew, thank you for your help.

    How can I change the data rate of the converter.  lets say we wish to configure the data to 100kbps? I had trouble finding this on the D/S, I see the if you are using pseudodiff it defaults to half its max data rate, down to 500kbps but if u have fullydifferential then you have the full 1Mbps.  Could you point me to say, changing the data rate down to 100kbps?  Many thanks.

  • 0 in reply to Jorge Vega
    TI__Guru 63196 points

    Hi Jorge,

    As with any SAR ADC, the sampling rate can be varied by scaling the input clock frequency and lengthening the acquisition and/or conversion times during each cycle. Section 7.9 Timing Characteristics in the data sheets lists the clock frequency range for each clock mode as well as the minimum acquisition and conversion time requirements. 

    Notice that the conversion time is a fixed number of tCLK periods. As you scale the input clock frequency, the conversion time will scale accordingly. 

    The acquisition time occurs near the end of the conversion cycle period. Figures 1 and 2 show which CLOCK falling edge corresponds to the beginning of the acquisition period. The end of the acquisition period is marked by the rising edge of CONVST. By lengthening the acquisition period, the external ADC drive circuit has more time to charge the internal sample-and-hold capacitors and reduces the required GBW of the drive amplifier.

    Make sure that you continue to satisfy all other timing requirements when scaling conversion and acquisition time.

    Best regards,

  • 0 in reply to Ryan Andrews
    Intellectual 300 points

    Hi Andrew.  Let me reflect back what we understood from your email:

    1. Lower the frequency and the acquisition TIME will increase proportionally.  This will have the consequence of REDUCING the sample rate.

    2. Extend the CONVST and this will result in more charging time for S/H internal caps of converter resulting in less current that needs to be drawn by OPA driving the reference pin and also FURTHER reducing the sampling rate.

    3. Bottom line: two knobs to reduce sampling frequency: CLOCK and CONVST.

    Did we get this correct? pls see image below.

    Can you guide me with the math that it takes to get the effective sampling rate if the frequency is reduced to 500kHz? The D/S shows in the timing section that it takes a FIXED 17.5 periods to convert the input signal.  So this means 17.5cycles x (1 / 500kHz) ... so to convert 17.5cycles it takes 17.5us.  Where do I go from here? Thanks in advance.

  • 0 in reply to Jorge Vega
    TI__Guru 63196 points

    Hi Percy,

    Increasing both the acquisition time and the conversion time will ultimately increase the conversion cycle period, which decreases the ADC sampling rate.

    You are correct when you say that slowing down the clock frequency increases the conversion time. However, the number of clocks that you are required to send is fixed. For Half-Clock Mode, the minimum conversion time is 17.5 clock periods because data is shifted out of the device on the clock rising edge. We need 18 rising edges to clock out all of the data. The first clock rising edge indicates the channel (CH0/1) and the second bit indicates ADC (A or B). The remaining 16 bits are the data.

    Decreasing the clock frequency will lengthen the conversion phase (tCONV) and this is better for reference voltage settling. The transient current spikes will be the same, but the time between each transient current spike will increase and allow for better reference settling. Overall, the average current on the reference input will reduce.

    When you increase the acquisition time, this has the effect of allowing better settling on the ADC input voltage (not the reference voltage). During the acquisition phase, the input voltage is charging the internal sample-and-hold capacitors. The reference voltage only sees a transient load during the conversion phase, not the acquisition phase.

    Best regards,