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DAC3283: DAC3283

Part Number: DAC3283
We are facing some issues related to DAC 3283.  Please let us know if there are any issues with the configuration setting.
DAC Clock = 224 MHz LVPECL
DATA Clock = 112 MHz LVDS
Desired Frequency = 70 MHz
Mode =+ Fs/4 Mixing
The issues are listed below.

1.       The desired frequency is 70 MHz. So we generated 14  MHz inside FPGA and sent to DAC 3283. Channel 1 cosine wave and Channel 2  sine wave using DDS in FPGA (ZYNQ7000) are sent to DAC alternatively. 

As mentioned in the datasheet rising edge of the DATA Clock MSB 8 bits and falling edge LSB 8 bits are sent. After Fs/4 mixing we are seeing both 56 (Fs/4)+14 =70 MHz and 56 (Fs/4) -14 = 42 MHz on the spectrum. Is it possible to generate only 70 MHz with the below configuration?





  • In your current setting you are setting the signal at +14 MHz, but there is also an image at -14 MHz.  When that spectrum is shifted by Fs/4 the negative image is coming to the positive side and thus you are seeing that signal; hence, what you describe is expected.

    To achieve just a 70 MHz tone you have some options, but you will need to modify your settings slightly.  One option is to run with no interpolation and keep the data rate at 224 MHz.  With this approach you have sufficient BW to create your signal directly at 70 MHz offset without using the coarse mixer.

    Another option is to use the Fs/2 coarse mixer and create the BB tone at 42 MHz.  With the mixing you will get -42 + 112 = 70 MHz and 42 + 112 = 154 MHz.  You will still have an unwanted signal but it will be at a higher frequency that may be more easily filtered.


  • As we are using complex mixing in Fs/4 mode I should be seeing only 70 MHz but not 42 MHz?

  • Is the BB pattern generated complex?  If you are using HSDC Pro to generate the BB pattern then you can select BB pattern to be complex.  On your FPGA then this is also required.  --RJH

  • Yes BB pattern generated is complex from FPGA. The output should be 70 MHz with Fs/4 mixing. Is the 42 MHz component in the spectrum due to timing issues or phase,gain imbalances?? 

  • I agree with you that if everything is working correctly then you should not see the image signal.  One possibility, if you are using your own FPGA and design, is that the timing or data packing is off by one sample between the I/Q streams.  We have had that type of problem before.  This effectively creates a phase mismatch which result in a large image signal.  You may be able to create a unique ramp pattern or similar from the FPGA and monitor the I/Q output to see if there are indeed any timing issues or sample imbalance issues.