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ADS6424: dclk and pclk are week

jacob sarusi
Prodigy 120 points
Part Number: ADS6424
Other Parts Discussed in Thread: ADS6422,

we have connected ads6422 with input clock lvpecl level (80M) we have the device parallel configuration.

looking at dclk and pclk we 240M 20mv p2p and 80M 80mv p2p

these signal are connected to latice fpga.

clarification:

The same configuration was used with ads6422 and worked perfectly.

the difference was the input clock which was connected using 40M cmos level through the clock baloon configuration as described in the evb.

whay using the faster device we get such a week dclk and pclk ?

what can we do if we are using parallel configuration ?

Thanks

Jacob

  • 0
    TI__Genius 12780 points

    Hi Jacob,

    One of our device experts is looking into your question, and will be back with you soon.

    Just so we understand correctly, you are no longer using a TI evaluation board, but have designed your own PCB? Are the ADC data/clock outputs connected the same way to the same FPGA? Are the data bits toggling, and are they at the same voltage levels? Are you able to share a schematic?

    Best Regards,

    Dan

  • 0 in reply to dBrock
    Prodigy 120 points
    Hi,
    We were using DEV board with ads6422.
    In accordance we developed our own board to fit our application. All was good. (In this board DCLK was 120M 100mvp2p and PCLK wa 40M 220mvp2p)
    We needed 80M sample rate therefore we changed the device to a compatible pinout and control ads6424 (we wanted to use 6423 but we couldn't find it available)
    In the previous board we used a CMOS level 40M oscilator connected to clkin SMA. IN the updated board, In order to be more efficiant we placed onboard an 80M lvpecl clock oscilator to drive clkin.
    da0 and da1 toggles 280mvp2p. (in ads6422 it toggles 430mvp2p)
    Notes: 
    We are using parallel configuration.
    All adc output are connected to FPGA.
  • 0 in reply to jacob sarusi
    TI__Expert 4880 points

    Jacob,

    I am a little confused by your description can you please explain to me which clocks you are referring to you when you say PCLK and DCLK? Though i don't completely understand what the issue might be, i did I notice what you said about being able to verify that the EVM works as expected with an LVCMOS clock input. But you are using a different clocking scheme for your custom board that is not working as expected. Is it possible to verify that the EVM works when using the clocking scheme you are attempting to use with your custom board? If so, that would be a good start. 

    Yusuf

  • 0 in reply to Yusuf%20Agoro
    TI__Expert 4880 points

    Havent heard anything back. Will close for now.