DAC5574: How to check DAC5574 work normal?

Chen,

Can you describe the complete sequence of commands used to attempt to update the DAC? There are a variety of methods to get this done, so I want to check the commands to ensure that this is being done correctly.

From a schematic perspective the device is fairly simple and the schematic looks fine.

Hi Kevin,

Our PIC engineer is off, can't provide what you need now. However, we need to fix this issue as soon as possible. Can you provide sample code of Verilog for check first?

Thank you.

Hi Kevin,

Please refer to attached file. 

Thanks!

Roger,

The frame structure looks correct though I think the text is missing some details. The I2C frame is expected to contain a start condition, the device-level address byte, a control byte, then the 16-bit data divided in an MS-Byte and LS-Byte.

The main item I was interested in discussing was the exact contents being written to the device. Page 14 shows the bit-field definitions for the control byte where the MSBs L1 and L2 control the update mechanism of the DAC. You will see that some of the update modes actually update a temporary internal register of the DAC without updating the output (L1 = 0 and L0 = 0). For the DAC output to update after the write L1/L0 should be set to 01.