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ADS1296R: Respiration question

Dane Zhang
Expert 4865 points
Part Number: ADS1296R
Other Parts Discussed in Thread: ADS1292R, ADS1294

As is shown in the picture, the application note says that blocking for a longer period in the respiration measurement results in less gain error. Then why can't we set the blocking period as long as possible(>150 for example).

  • 0 in reply to Dane Zhang
    TI__Guru 61336 points

    Hi Dane,

    That's a good question.

    As the app note explains, we implement blocking techniques for two reasons:

    1. To account for the phase delay between the modulated input signal and the internal demodulation clock
    2. To ignore the RC rise/fall time associated with the beginning of each one-half modulation clock period

    For respiration measurements, the signal of interest has a period that is much larger than one-half of the modulation clock period. Theoretically, you can block almost the entire time (i.e. 179 degrees) and only pass through the final settled value. However, as shown in Figures 100 and 101 in the data sheet, longer blocking times produce higher noise. My guess is that the internal design requires a minimum time needed for the input signal to settle after the blocking is removed. 

    Best regards,

  • 0 in reply to Ryan Andrews
    TI__Expert 4865 points

    Hi Ryan，

    Thank you for your explanation. There' re few more questions:

    1. Is the settle time equivalent to the sampling time of the ADC?

    2.Figures 100 and 101 in the data sheet shows that longer blocking time produce higher noise, then is the results and conclusion coming from the experiment?( Different circuit has different optimal phase shift? 

  • 0 in reply to Dane Zhang
    TI__Guru 61336 points

    Hi Dane,

    I wouldn't say that the settling time is equivalent to the sampling time of the ADC. Remember that the ADS1296R uses a delta-sigma ADC architecture and is continuously sampling. I'll try to consult the design team to understand why the maximum blocking period is 157.5 degrees.

    Remember that these are using the internal respiration control signals. External signals for the modulation clock and blocking control can be provided externally as well. This would allow the customer to experiment with blocking phase amounts other than what is offered in the register settings, but the recommended maximum is still 157.5 degrees. Please refer to section 9.3.1.7.8.3 in the data sheet.

    Yes, the conclusion that longer blocking time produces higher noise came from empirically analyzing this feature on the bench.

    Best regards,

  • 0 in reply to Ryan Andrews
    TI__Expert 4865 points

    Hi Ryan,

    Thank you for your explanation

    1.  I wonder why the rise/fall time will effect the noise. Theoretically, when encountered with the rise/fall period, both the signal and the noise will decrease. Could you explain why will the noise increase while the signal gain is attenuated when encountered with the rise/fall time?

    2.As is shown in the picture, why there is a sharp increase of the noise when PGA=3 and the baseline impedance is around 9155Ohm (modulation clock=64KHz).

    Thanks

  • 0 in reply to Dane Zhang
    TI__Guru 61336 points

    Hello Dane,

    I've discussed the maximum blocking time with the design team and the limit in the data sheet is suggested purely based on our observations of increased noise. It's difficult to explain exactly where this noise is coming from, but most likely it has to do with the settling of the input signal at the modulator input when the blocking is removed.

    Between the blocking+demodulation stage and the delta-sigma modulator input is a differential capacitor. In the ADS1292R, this capacitor is placed externally between the PGA outputs (about 47 nF). On the ADS1294/6/8, this capacitor is internal and larger (about 100 nF). Each time the blocking signal goes low, the output of the demodulation circuit connects the demodulated signal to the differential capacitor ("low-pass filter" in the figure below).

    Meanwhile, the delta-sigma modulator is continuously sampling the voltage across this differential capacitor. The longer you block, the less time the demodulated signal has to settle to a final value. This unsettled voltage will be held during the next half of the modulation clock period until the block is removed again.

    The noise plotted in Figure 79 is measured data. We do not have a clear explanation as to why this happens specifically for Gain = 3 and we provide the results to support our recommended settings for best performance.

    Best regards,