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Original question:

ADC124S051-timing of SCLK and CS

ADC104S021: t_CLH clarification

Brett Kutscher
Prodigy 130 points
Part Number: ADC104S021


Page 5 describes T_CLH as the hold time between SCLK Low (which I assume means the falling edge) to CS_N Falling Edge.  The timing diagram (Figure 5, Page 7) Shows t_CLH to be the delay between the falling edge of CS_N and the rising edge of SCLK.  Which is correct?  Are there any limitations on the SCLK falling edge to CS_N falling edge timing?  A previous E2E answer ("ADC124S051-timing of SCLK and CS") implied there are none (is it a spec sheet typo, or am I wildly confused).

Thank you,

Brett

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    TI__Guru**** 181701 points

    Hi Brett,

    Welcome to our e2e forum!  The picture and text is a little confusing perhaps, but there is more detail on page 17 that will help to clarify the situation.  Page 5 is talking about the physical state of the SCLK (logic 0) rather than a falling SCLK edge.  Essentially the ADS104S021 is meant to be used with an SPI interface where the SCLK dwells high - logic 1 or CPOL=1, so in that case you should not run into timing issues with the chip select and SCLK timing.  If you are using a GPIO for /CS, you might want to add a little delay before starting the data transfer.