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ADC104S021: Running without CS_N

Part Number: ADC104S021


I am trying to save pins in my project.  One option I'm considering is to try to run the ADC104S021 without active CS_N control (either by hard tieing it to ground, tieing it to a power-up reset chip, or by tieing it to a one-shot triggered by the falling edge of SCLK).  To this end, I have two questions:

1) Assuming I have properly synched myself to the stream, can I continuously read the device by sending 16 bit clocks (and appropriate DIN configuration messages) without ever toggling the CS_N line?

2) Will the chip reset automatically if I let SCLK go idle for a period of time even if CS_N is constantly asserted?  How long?

Thank you,

Brett

  • Hi again Brett,

    You do need the first CS high to low transition on the ADC104S021 - which you could do with a supervisor circuit or one-shot trigger.  Not sure exactly what you mean by 'reset' in this case, if you let the SCLK idle, the ADC will go into a power down state and it will automatically recover or 'reset' from that.  If you get out of sync somehow (send more or less than 16 clocks per conversion cycle for instance), you would have to trigger a reset of the serial interface by toggling /CS again. 

  • Thanks, Tom.

    Do you know how long I would need to let SCLK idle for in order to go into a power down state?  If I get out of sync on my serial stream, would going into idle this way resync the chip when SCLK started again (without toggling /CS)?

    Also, my apologies -- the answer to (1) was in the data sheet (explicitly in the power supply considerations section and in figure 3)

    Brett

  • Hi Brett,

    The ADC104S021 enters its power down state with the 16th falling SCLK edge and remains in that state until the next falling SCLK, so you don't need to worry about how long the clock is idle.  The longer you leave it idle, the lower the overall power consumption.  The only way you could resync, would be to toggle /CS unfortunately.