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DAC8568: SOME PROBLEMS

Mojtaba pourdara
Prodigy 230 points
Part Number: DAC8568

Hi dear 

I have some problems with the dac8568 datasheet. 

1- what does mean the Grade A,B,C or D in the datasheet. is it an option when buying the device or a setting that we could change it?

2-what's the difference between flexible mode and static mode when we power up internal reference? in both of them we have the same options in the datasheet. it just difference in bit's we should send to shift register.

3- how can we choose synchronous or Asynchronous mode for load data?

4- what does "Update selected DAC registers" do in page 36 of datasheet? what's the different with writing to such a Register? the DACs are updated on the 32 falling edge of the SCLK or falling edge of /LDAC so what does this code do?

5- what's the different between 3 different power down mode? and if we want a channel to don't send any current for a short time period it's better to power down this channel or write 00000000 to this channel and if choosing power down, which mode is better for us?

  • 0
    TI__Mastermind 46290 points

    Mojtaba,

    Uttama from my team will get back to you tomorrow.

  • 0 in reply to Kevin Duke
    TI__Guru 53693 points

    Hi Mojtaba,

    1. Here are the grades:

    Grade A: Lower precision reference (voltage and drift), DACs start at zero-scale

    Grade B: Lower precision reference, DACs start at mid-scale

    Grade C: Higher precision reference, DACs start at zero-scale

    Grade D: Higher precision reference, DACs start at mid-scale

    2. In static mode, the reference will be shut down when the DACs are shutdown and enabled when the DACs are enabled.  In flexible mode, you can enable the reference which will stay enabled on even if the DACs are shutdown.  This allows you to use the reference for external functions without worrying about the state of the DAC channels.

    3. For synchronous mode, the LDAC pin should be connected to GND. For asynchronous mode, the data is latched on the falling edge of LDAC.

    4. This device uses a double-buffer topology, meaning that there is an input register and a DAC register.  The DAC register is the value that is currently being outputted by the DAC.  The input register is just a data storage register.  If you are using the device in asynchronous mode, you should write to the input register.  This will store the value until something causing the input register value to be copied into the DAC register value, which will update the DAC.  This could be an LDAC edge or software LDAC command. You can also bypass this by writing directly to the DAC register.

    If you are in synchronous mode, the input register value is automatically copied to the DAC registers at the end of the SPI command.   

    5. If you do not want current output in the DAC, then you should use the High-Z mode.  This makes the output high impedance (floating).  The other power-down modes connect the output to ground with either a 1kΩ or 100kΩ resistor.  If you set the DAC output to code 0, it will drive the output to 0V, so it could potentially source current.

    Thanks,

    Paul