Figure 1 "ADC121S021 Serial Timing Diagram" shows SCLK idling high; that is, it shows SCLK as already high when nCS goes low at the start of a data transfer, and it shows SCLK being brought high at the end of the data transfer prior to nCS being brought high.
We're interested in the behavior of the ADC121S021 when SCLK idles low, instead.
There is a mention in the data sheet that "If CS goes low before the rising edge of SCLK, an additional (fourth) zero bit may be captured by the next falling edge of SCLK." (Instead of the documented three zero bits at the start of a data transfer.)
How dependable is this behavior? Can we expect that getting four zero bits is reliably and dependably the case when SCLK is low prior to and as we lower nCS? Does this behavior depend upon any other conditions (such as how much time there is between when we lower nCS and when we raise SCLK for the first time)?
--thx