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DAC34H84EVM: not generating required clock

Part Number: DAC34H84EVM
Other Parts Discussed in Thread: CDCE62005, DAC34H84
Hi
I want to use DAC34H84 EVM at maximum 1.25 GSa/s through xilinx fmc adapter. I am using CDCE62005 for DACCLK generation. My current configuration for DACCLK is attached.
With my current configuration I am getting Y3:FPGACLK of around 384 MHz with divider value set to 2. When I set divider value to 1, the clock disappears. 
I also tried changing loop filter values but no use.
What should be the CDCE62005 clock configuration to achieve maximum sampling rate of 1.25 GSa/s?
  • Hi,

    I am not an expert for the CDCE62005. You will need to contact clock/timing product support for more detail. The VCO of the CDCE62005 does not support any multiples of 1.25GSPS, and therefore, you will need to use external clock mode to test 1.25GSPS mode

    We have some example file for 983.04MSPS evaluation if you would like. They are in the default DAC348x EVM GUI folder:

    C:\Program Files (x86)\Texas Instruments\DAC348x\EVM Configuration File Released\DAC34H84\Example CDCE62005 PLL Configuration

    Again, for more question on the CDCE62005 product, please contact the clocks/timing product support.