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TSW40RF82EVM: Schematic of TSW40RF82EVM

Part Number: TSW40RF82EVM

Can you please provide schematics of 



  • Channamallesh,

    The schematic is attached. FYI, the board design files can usually be found under the product folder on the TI website.




  • Thank you Jim. Design files are not available for this board on TI website. 

    I have a couple of questions. I see that balun start frequency of TC1-1-43X-2+ is 650 MHz. I would like to use the device for frequencies from 100 MHz to 1200 MHz. I can use connectors J43 and J44 to connect to a balun. Do you have any suggestions for a balun which will work very well with the ADC? 

    Also, section 5.3.1 of the user manual states that serdes rate can not be greater than 5 Gbps. What is the reason behind this? Is this the limitation of FPGA? I am using KCU105. Will it work at higher serdes rate with KCU105?

    Please let me know.


  • Channamallesh,

    Yes, you can use those SMA's to bring in an analog input. You will have to move two resistors to allow this. You can use a transformer board made by TI called the "ADC-WB-BB" that has a transformer with a bandwidth from 4.5MHz to 3GHz. You can find this on the TI website.

    The ini files called out in the User Guide points to the firmware file called "TSW14J56REVD_FIRMWARE.rbf" which only supports a max serdes rate in transceiver mode is < 5Gbps as the firmware uses external DDR memory for both RX and TX (DDR throughput issues occur at higher SERDES rates).


    But we have tested transceiver operation with TSW14J56REVD_BRAM_ADC_DAC_DDR_128K_XCVR_FIRMWARE.rbf till 10Gbps as the capture and generation uses separate memory, ADC capture supported with BRAM memory and DAC generation supported with external DDR memory. If you modify the ini file to use this other firmware, you can operate the board at a higher serdes lane rate.