ADC34J43: Data converters forum

Hi Diverger,

1. My target sample rate is 80M. So, the clock goes to the 'CLKP' and 'CLKM' should be 80MHz, right?
   Yes, this is correct. With our FPGA data capture card, we also need to provide an FPGA clock that is 2X that of the sampling clock. 
2. I find the ADC34J43EVM use a 100MHz VCXO, so I try to get exatly 80MHz output in PLLatinum Sim and failed as below. So, if I want to eval ADC34J43 at 80MHz on this board, I must enable the internal divider, right?

In the attached file, there are register writes that set the LMK04828 (very similar to the LMK04832) to this mode. So basically, we set the PLL output to a frequency that can be divided down to 160MHz and 80 MHz. You can also download the GUI for the ADC34J43EVM, and load these files in simulation mode (no EVM required), and you can see what the LMK dividers are being set to.7178.Configuration Files.zip

1. Are there any docs about how to use PLLatinum?

I do not directly support the PLLatinum tool, so I will need to direct you to post a new thread on the HSDC-HSSC forum. I would suggest taking a look at the software tool TICS Pro which also supports configuration of the LMK04832.

http://www.ti.com/tool/TICSPRO-SW\

Best Regards,

Dan