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ADC12D1620QML-SP: Additive Jitter from ADC to Perform FPGA Timing Analysis

John Roy94
Prodigy 180 points

Part Number: ADC12D1620QML-SP

Hello, 

What is the best way to determine the jitter that the output sample clock  (DCKI or DCKQ) will have when driven from the ADC? We are performing a timing analysis for the data interface to the FPGA and need to know how the ADC will behave with a given input sample clock w/associated jitter.

Any help here is appreciated.

Thanks

John

  • 0
    TI__Guru* 91947 points

    John,

    We are looking into this.

    Regards,

    Jim

  • 0
    TI__Mastermind 45670 points

    Hi John,

    The output data clock (DCLKI/Q) and input sample clock (CLK+/-) are not associated in terms of jitter performance. They are independent.

    The DCLK specifications given in the datasheet on page 23, should provide enough information to bound the timing analysis.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 180 points

    Hi Rob, 

    I'm not sure that that is the timing information that I need. Let me clarify, we are using the ADC clock (DCKI/DCKQ) for the internal logic to the FPGA. Given we are using the output clock from the ADC, we need to know what jitter will be present on the DCLK signals after the ADC divides it down internally. We are using the ADC in non-DES mode w/DDR 0 degree phase, and 1:2 demux. We expect a 400MHz clock to be driven into the FPGA. There has to be some relationship between the input sample clock to the output DCLK signals. 

    We need to know the jitter on this clock as it will be used as a reference clock to a PLL inside the FPGA.  The jitter on the input clock (i.e. DCLK jitter) will directly affect the jitter on the output clock (internal to the FPGA).

    The clock to data relationship will be adjusted using a calibration routine to center the clock in the data window. That is a separate topic to this thread.

    Thanks,
    John

  • 0 in reply to John Roy94
    TI__Mastermind 45670 points

    Hi John,

    Thank you for the details. Yes, I understand your question. Unfortunately, there typically isn't much jitter information taken from the DCLK outputs of the ADC in terms of jitter performance. After some checking around and talking to the designers, this information isn't available. I have attached a screen shot of the output to verify that this output clock is very clean and shouldn't have much contribution on the internal PLL inside the FPGA.

    Another way to prove this out is to use an very clean signal generator as the clock source, connect that to the FPGA and benchmark or baseline the FPGA's internal PLL performance. Then use the ADC's DCLK output to see the difference.

    Hope that helps.

    Regards,

    Rob