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DAC37J84: DAC not recognising bcbc characters in CGS

Part Number: DAC37J84

I am interfacing DAC37J84 EVM with Xilinx ZCU102 Zynq board. I am seeing in chipscope that FPGA is sending "bcbc" characters for doing CGS. But DAC is not recognising "bcbc" characters and toggling SYNC accordingly. 

If I check the box "TX doesn't support ILAS" in JESD Block tab of DAC GUI and force FPGA to send the data, then I am getting output.

Below is my DAC and JESD configuration:

LMFS: 2441

DAC input rate: 250MSPS

Interpolation: 4x

Lane rate: 10Gbps

Request your help in resolving the issue.



  • Kiran,

    Upon recognition of the K28.5 (BCBC chars), the DAC will pull SYNC to logic HI and start checking for ILAS. If the ILAS is not passed or any other error occurs, the DAC will pull SYNC low again.

    I have answered your question regarding potentially ignoring ILAS to continue with the data phase in other forum thread. In order to pass ILAS (if you choose not to ignore), you will have to ensure each ILAS parameters are programmed correctly on *BOTH FPGA and DAC IP". Only programming one side is not sufficient as it is an ID check (and really serves no other purpose).

    Please refer to the other thread for detail.