I am interfacing DAC37J84 EVM with Xilinx ZCU102 Zynq board. I am seeing in chipscope that FPGA is sending "bcbc" characters for doing CGS. But DAC is not recognising "bcbc" characters and toggling SYNC accordingly.
If I check the box "TX doesn't support ILAS" in JESD Block tab of DAC GUI and force FPGA to send the data, then I am getting output.
Below is my DAC and JESD configuration:
DAC input rate: 250MSPS
Lane rate: 10Gbps
Request your help in resolving the issue.