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DAC37J84: Some of the K values are not working

Part Number: DAC37J84

I used DAC37J84 EVM with Xilinx Zynq ZCU102 board. Below is my DAC configuration.

LMFS: 2441

DAC input rate: 250MSPS

Lane rate: 10Gbps

Interpolation: 4x

I observed that if I set K = 5 or 10 or 20 or 28, I am getting output.

For each of the K value above, I am changing SYSREF frequency according to "DAC3xJ8x Device Initialization and SYSREF Configuration". 

But if I set K = 31 or 32, I am not getting any output.

Request your help in resolving this.



  • Kiran,

    You will need to be sure that the K value on both DAC IP and FPGA IP are changed, and also the SYSREF appling to the FPGA and the DAC are changed accordingly. 

    SYSREF calculation and parameters are the following:

    Also, it is possible changing the K value will also change the optimal RBD (release buffer point) for the DAC IP. You will need to fine tune it. Changing K effectively changes the multi-frame period. JESD204 committee recommends to set K large enough to cover the latency variation for each lane. If you changed K, you will need to tune RBD also.

    Please see below app note, figure 2, that talks about RBD release point: