DDC232: Issue regarding readout of configuration register

Hi,

Thank you for your prompt and helpful inputs.

As per the pattern you have given, I am getting the 4 bits die ID as 0100, is it correct value? In some other thread in the forum I noticed, it was written that it should be 0001.

What does it depend upon?

Regards,

Shib Shankar

Hi Praveen,

Thank you. This explains the config readback I am getting for the said part no.

But I was also using an older part no. DDC232CGXGT in the daisy chain. It was giving pattern like <12 bits config><4 bits die ID(0001)>< zeros><72 bits test pattern> ...this repeated twice - the initial 4 bits zero were not there. In the datasheet also it is given like that only. Is there any new revision of the device datasheet available?

I am facing issue in data retrieval also. I am using 7 DDCs in cascade, 20 DCLK (20 MHz) pulses are sent for each channel to retrieve the data (total 20*32*7 clocks for acquiring one side data). The readout pattern is showing some random behavior. From the readout patterns it looks like going into 16 bits mode randomly, and the pattern getting shifted and disturbed since I am expecting 20 bits readout with the given clock pulses.

Regards,

Shib Shankar

Hi Shib,

Yes, for the older part # DDC232CGXG die, read back in (20 bit format mode) will be:

640 bits total: <12 bits CFG register><4 bits die ID = 0001><232 bits of 0><72 bits of test pattern (30F066012480F69055h)><12 bits CFG register><4 bits die ID = 0001><232 bits of 0><72 bits of test pattern (30F066012480F69055h)>

We will look into updating the datasheet with the correct read back words.

Regarding the data retrieval issue, below are some questions and suggestions to help you debug the issue.

1. What is the integration time (tint)?

2. What is the CLK frequency?

3. How are you configuring the 7 DDCs: dedicated DIN_CFG and CLK_CFG pins or common across 7 DDCs?

4. Are you daisy-chaining the configuration readback?

5. Have you read back and verified the configuration word for all 7 DDCs?

6. Are you performing the data retrieval before CONV toggles or after CONV toggles?

7. Are you able to identify the DDC(s) that you are suspecting to cause the issue?

8. Can you confirm that the DIN_CFG and CLK_CFG are not toggling during the data retrieval operations?

9. How are you verifying the data? Are you feeding in some known DC current across each DDCs?

Hi Praveen,

Thanks. Your clarification explains the readback of configurations for DDC232CGXGT and DDC232CZXGT. I will have to use all new version ICs only in a chain.

Now the problem is data retrieval only. The inputs you have mentioned are as follows:

1. Integration time is 100 us (Non-continuous mode)

2. CLK = 5 MHz, DCLK = 20 MHz

3. Common DIN_CFG and CLK_CFG are going to all 7 DDCs through multi-drop distribution.

4. Configuration readback is daisy chained as in the case of data readback (I am sending 7*640 DCLK pulses).
5. Configuration readback of all 7 DDCs are done and found OK.

6. Data retrieval is done after CONV toggles.

7. It is happening mostly with all the DDCs of DDC232CZXGT part no. For the older part this issue is not coming. I am suspecting that there is some difference in readout protocol of the two devices.

8. DIN_CFG and CLK_CFG are not toggling during data retrieval. It is taken care of.

9. With some known current source also the readbacks were seen. 

The data I have verified by recording the DOUT w.r.t. DCLK on oscilloscope. There is random variation of orders of magnitude. Can you share your mail id please? Here there is no provision to attach image files.

I can show you what kind of readbacks I am getting for DDC232CGXGT  and DDC232CZXGT.

Regards,

Shib Shankar

Shib,

Please send your data retrieval images to ddcxxx-support@list.ti.com along with a reference to this e2e post.

Hi Praveen,

I have sent the images. Please check.

Regards,

Shib

Hi Shib,

We have received your email and processing it.

We will get back to you by early next week.

Thank you, Praveen.

Hi Praveen,

Could you get any inputs regarding the data readout issues?

What I am noticing is that, when I am reading at DCLK = 10 MHz, it is behaving OK.

But when I am reading at DCLK = 20 MHz by boosting clock frequency (I measured, it is pretty stable, varying from 19.7 MHz to 20.3 MHz) using internal PLL of FPGA, it is misbehaving, data are coming all random.

Even if the readout is correct initially at start of acquisition, within few minutes (or sometimes after long time also) it is going into that random mode.

What is the relation with the DCLK frequency at the higher side and how much it is dependent on the stability and other qualities of DCLK?

Regards,

Shib Shankar

Hi,

Could you get any info about the data readout problem?

Regards,

Shib Shankar

Hi Shib,

Apologize for the delay in the response.

I discussed with the systems expert and we have not come across any readout problems at the max DCLK.

You mentioned that you noticed this issue in all the 7 DDC devices in your daisy chain. Is that correct?

Do you also notice the issue on multiple boards?

Would it be possible to reduce the number of devices in your scan chain and check if the issue occurs?

Also, have you tried only 2 frequencies like 10MHz and 20MHz? or have you checked frequencies closer to 20 MHz?

Hi Praveen,

I just checked with reduced number of devices. Upto 2-3 devices, the behaviour is OK.

But when I am connecting 4 devices, it is working OK for some time, but after about 5-10 minutes, it is going into the random state.

I have checked with changing the units, it is behaving same for different pieces of the IC.

I am sending some more snapshots on that same mail, please see if you can give some clue, what is happening.

Regards,

Shib Shankar