DAC39J84EVM: HSCV pro

jeff chen1

Part Number: DAC39J84EVM

Hi,

DAC38J93evm + TSW14J10evm + vc707, the setup as: onboard clock mode, 4 serdes lanes with 1 interpolate, LMFS 4421, line rate 7372.8M, clk0 div 8, clk12 div 16, on board PLL1/2 led lit, suppose locked?

but the three lock alarm DAC alarm tab page are all green, DAC sync led is on, JEDS mode is on, system clk div and JEDS core clk div are blinking, but refe clk div is solid instead blinking, see plots attached,

need help.

Thanks,

Jeff

over 4 years ago

0 jim s over 4 years ago

TI__Guru* 91947 points

Jeff,

There was no plots attached. Can you please send screen shots of the DAC GUI showing all of your settings plus the alarm status?

Regards,

Jim

0 jeff chen1 over 4 years ago in reply to jim s

Prodigy 200 points

Hi, Jim,

I did paste, but disappeared.

Thanks,

Jeff

0 jeff chen1 over 4 years ago in reply to jeff chen1

Prodigy 200 points

screen shot.docx

0 jeff chen1 over 4 years ago in reply to jeff chen1

Prodigy 200 points

Hi, Jim,

the LED on the VC707: on, off, off, off, on, flesh, flesh, flesh. No data output.

Thanks

Jeff

0 jim s over 4 years ago in reply to jeff chen1

TI__Guru* 91947 points

DAC38J84_442_491p52.pptxJeff,

I think your clock dividers are incorrect. Please try using the settings shown in the attached example. The DAC clock is different but close enough where I think these settings will work for you.

Regards,

Jim

0 jeff chen1 over 4 years ago in reply to jim s

Prodigy 200 points

Thanks, Jim,

the clock setting from your document solved the problem, but which document explains these setting? since there are so many combinations exist.

Thanks,

Jeff

0 jim s over 4 years ago in reply to jeff chen1

TI__Guru* 91947 points

Jeff,

Follow the DAC User's guide for the most part but when HSDC Pro displays the required FPGA frequency, make sure the LMK output divider is set properly for this setting. The TSW14J10EVM User's Guide also talks about this as well as what frequency the other FPGA clock (core clock) needs to be set to based on the serdes lane rate.

Regards,

Jim

Data converters

Data converters forum

DAC39J84EVM: HSCV pro