Other Parts Discussed in Thread: DAC39J84
Hi, support,
the base band out put is not stable, is there any trigger signal can be used for frame synchronization, either in vc707 or DAC39J84evm?
Thanks,
Jeff Chen
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Hi, support,
the base band out put is not stable, is there any trigger signal can be used for frame synchronization, either in vc707 or DAC39J84evm?
Thanks,
Jeff Chen
Hi Jeff Chen,
We are looking into your question and will get back to you.
Regards,
Vijay
Jeff,
Due to the serdes going through 2 connectors, at this high rate, the Xilinx equalization probably needs to be adjusted, which cannot be done with this firmware. If you operate in 8411 mode, the serdes rate is reduced by 50% and you should not have a problem. In this mode, the CLKout 0 and 1 divider should be set to 16 and the CLKout 12 and 13 divider should be set to 32.
Regards,
Jim
10MHz_4CH.csvJeff,
You can generate test patterns using a .csv format. I have attached an example. Each column is for data for each channel. For a DAC39J84, there will be 4 columns. The data is signed integer format. This example will provide a 10MHz tone for each channel when sampling at the correct frequency. I do not remember what that was for this file.
If you generate a test file using the I/Q Multitone Generator in the lower left of the HSDC Pro GUI, after it is created, in the top left of the GUI you can click on "File" then "Save Integer (I32) Codes as CSV File" to save the data. This will also provide an example of what the test pattern should look like.
Regards,
Jim
Hi, Jim,
Since the paths on DAC39J84evm from DAC output ports to SMA ports are too long for out test platform, we need directly use TI design package to design our board to fit our test, is that legal? will software still work?
Thanks,
Jeff Chen