• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 225 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

ADC32RF45: Behavioral RTL (VHDL or Verilog Model)

ADC32RF45: ADC12J4000

Alexei Lomakin
Prodigy 20 points
Part Number: ADC32RF45
Other Parts Discussed in Thread: ADC12J4000

Hi,

I am looking for a simulation models (either VHDL or Verilog) for ADC32RF45 and ADC12J4000.

I need  behavioral models to help me connecting  ADC to ASIC we are developing that would be interfacing to multiple ADCs chips.

Any recommendations for the JESD204B IP vendor to be compatible with TI ADC?

Thank you for any help.

Best regards,

Alexei Lomakin

MIT Lincoln Laboratory

alexei.lomakin@ll.mit.edu

  • 0
    TI__Guru* 91947 points

    Alexei,

    Both parts have IBIS and IBIS-AMI models available on the product folder on the TI website. Intel (formally Altera) and Xilinx have JESD204B IP that will work with both of these parts.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 20 points

    Hi Jim,

    Thank you for your reply. Unfortunately IBIS model will not work.

    I do not need model for the PCB signal integrity modeling yet.

    I am working on custom 14nm ASIC and need RTL VHDL or Verilog model that will work with ModelSim or QuestaSim.

    Also, I cannot use Xilinx or Intel/Alter IP for the custom ASIC. Both FPGA vendors provide IPs for FPGAs only.

    But your suggestion helped. Xilinx has 3rd party provider for the JESD204B IP. I will contact them.

    Thank you,

    Alexei