• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 47 subscribers
  • Views 555 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS1235: ADS1235

Eyal Bortman
Prodigy 30 points

Part Number: ADS1235
Other Parts Discussed in Thread: ADS1261

Hello TI team

Could you please advise what is the ettling time of the ADS1235 multiplexer ?

Assuming that the chip is working in continuous mode  and taking into consideration :

  1. The conversion time listed in table 6
  2. The delay time configuration
  3. The communication time for setting the correct channel and triggering the sampling

Are there any other factors that need to be taken into account ?

Could you please provide a rough calculation of the settling time with
sample rate of 400 sps , Sync2 , 2 channels multiplexing , chop disabled ,

What is the maximal throughput available under these conditions ?

Thanks

  • 0
    TI__Mastermind 44760 points

    Hi Eyal,

    I don't have any data specific to the ADS1235 multiplexer, but I would estimate that settles somewhere on the order of 1 us or less. I believe the PGA settling is longer, but is well accounted for by the default conversion start latency of 50 us.

    The conversion latency and the SPI communication time required to change channels will be the main limits to data throughput. The digital filters of the ADS1235 are the same as the ADS1261, so you can use the http://www.ti.com/tool/ADS1261-EXCEL-CALC-TOOL to determine the conversion latency for any given filter type, data rate, chop mode, or conversion start latency.

    For 400 SPS, SINC2 filter, CHOP disabled, and the default 50 us conversion start latency, the overall conversion latency is 5.43 ms (or about 184.33 SPS). To account for the SPI communication delay to switch channel, you can estimate it by multiplying your SCLK period by the number of command bytes (2 no CRC, or 4 in CRC mode) and then add some extra time to account for your microcontroller's delay time to service the /DRDY interrupt and set the /CS pin low), which will probably be on the order of a few microseconds.

    Adding about 6 us to 5.43 ms, you can probably expect a maximum data rate of about 183.9 SPS in the above mode.