DAC3283: Driving DAC3283 clock inputs with LVDS (versus LVPECL)

Hello, 

I am changing my design's topology to provide the OSTR signal from a Xilinx 7 series FPGA versus a PLL that can support LVPECL. (The DAC_CLK 800MHz will still be provided via the PLL's 800 MHz LVPECL)

Xilinx 7 series FPGA's only support LVDS_25. 

I see that other parts in the TI's data conversion family can support LVDS or LVPECL inputs based upon the termination used. Specifically, the ADS62p49 can be driven with this topology with LVDS.

An on-semi appnote on the same topic uses this topology:

Any advice would be appreciated.