Other Parts Discussed in Thread: ADS62P49
I am changing my design's topology to provide the OSTR signal from a Xilinx 7 series FPGA versus a PLL that can support LVPECL. (The DAC_CLK 800MHz will still be provided via the PLL's 800 MHz LVPECL)
Xilinx 7 series FPGA's only support LVDS_25.
An on-semi appnote on the same topic uses this topology:
Any advice would be appreciated.