I have an issue with DAC5687-EP. The parallel data, all control signals from FPGA.
1st. Tried to output a 12kHz sine wave, but the output signal is distorted and the frequency is not 12kHz, is around 8.2kHz.
2nd. When tried to output 27.6kHz sine wave, the output is correct.
CLK 1 =276kHz, CLK 2=2.208MHz. PLL VDD is tied to GND, Use external voltage reference (1.2V).
IOUTB1 & IOUT2 are pulled to analog 3.3V through two 50Ohm resistors.
Below are some registers' setting:
1. DAC B operation, DAC A sleep; Register x00h = "10000011".
2. FIR Interpolation: x8 ; Register X01h = "00001101".
3. Dual Clock Mode; Register X02h = "00100000".
4. NCO disabled; Register X03h = "00000000".
5. 4 pin serial interface; Register X04h = "10000000".
6. DAC B gain[11:8]="1100"; Register X19h = "00001100".
Can you tell me what is the root cause? Is there a minimum output signal frequency limitation?
Your help is very appreciated!