Other Parts Discussed in Thread: DAC39J84, , DAC38J84
I am having trouble getting SPI to work through the FMC path on the DAC39j84 evaluation board.
I am seeing the correct inputs to the CPLD by probing through an oscilloscope on the CPLD itself. FMC_SCLK, FMC_SEN_DAC, and FMC_SDIO are all showing up on the CPLD inputs as expected.
I made sure to follow the DAC39J84EVM user guide and ensure that the jumpers on the board are in the correct position for SPI transaction through the FMC, as well as the CPLD power sources. Note that SPI transactions through USB (when the jumpers are placed in their appropriate positions) seems to work fine. It's the FMC SPI that I'm having trouble with.
On the output of the CPLD, I am seeing the DAC_SCLK and DAC_SDIO behave correctly, however I do not see DAC_SDENB or DAC_SDO working correctly. More specifically, DAC_SDENB is held high and does not change at all, even though on the input to the CPLD the correct input.
To probe, I used the physical pin going into and coming out of the CPLD package since I don't know what the pin assignment is for the JTAG header that is supposed to show the SPI lines. The documentation (schematics and user guide) on pin mapping and what the CPLD is doing is not complete, since it doesn't mention what the pins correspond to, and what the internal routing of the CPLD is.
I did find the CPLD verilog file on the TI E2E forums for the DAC38J84 (
). It is probably similar to the file that I'm missing, but there are pins that are missing from it that are mentioned in the DAC39J84 schematic (such as DAC_RESET).
Furthermore, when probing the CPLD, I see that the DAC_RESET pin is periodically oscillating when I send my SPI command over the FMC connection. Is this why I can't see DAC_SDENB and therefore the DAC is not responding to my SPI command? Where does this reset come from? This would be a little more clear if it was possible to get access to the DAC39J84 EVM CPLD verilog file, so that I could see what the routing logic is and then debug from there.
Having this file would really help understand the evaluation board and determine what is going wrong in my SPI transaction, which otherwise looks like it should work if it wasn't for the mysterious CPLD in between the FMC and the DAC.
