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TLC7524: Is there a simple way to generate a non symmetric wave pattern

Part Number: TLC7524

I am using this component with a Vref of -9v. I am using the Figure4 configuration in the pdf. Is there a simple modification of this schematic to generate -3v to +9V utilizing all 8 bits of the TLC7524?

  • Hi Doug,

    I will get something for you on Monday.

    Thanks,

    Paul

  • Looks like you can get what you want by adjusting the resistors in the output stage.

    TLC7524.TSC

  • Paul,
     I want to thank both you and TINA for helping me with this exercise. It should give me ~(10/200)V  resolution in the positive range.

    Doug

  • When I use TINA, my voltage follows the binary logic as one would expect. However, on my PCB, the voltage follows the trend of the DIO pattern but not explicitly. For example the voltage output at DIO=16 is greater than the voltage at DIO=17. We got this result by mapping/reading  the DIO pins after we drove them to the correct l logic value respectively. My voltage output values look as if the chip is mislabeled or the resistors within the ladder are not R and 2R. Any ideas?

  • Hi Doug,

    I think I would first confirm the basics.  Are the logic lines absolutely correctly connected? For example, if the last two bits were reversed you could see that behavior.  I can't count how many times I have done this...

    I would also verify that the pinout on the schematic, footprint and layout all match.

    Finally, verify the voltage on the reference.  You can see that the resistive load on the reference is code dependent, so the current demand of the reference changes.  If the reference is some high-impedance source you could see this behavior as well.

    Thanks,

    Paul