ADS8664: tHT_CKDO value at fSCLK=2MHz

Ryo Akashi

Expert 8950 points

Part Number: ADS8664

Hello experts,

I got question from customer.

In datasheet "7.6 Timing Requirements: Serial Interface", there is desctiption of tHT_CKDO = 10nsec(TYP).

This test condition is fSAMPLE=500kSPS.

If customer set fSCLK = 2MHz, tHT_CKDO value will change?

They will connect MCU which has requirement of SDO hold time=40nsec.

Thanks and best regards,

Ryo Akashi

over 4 years ago

0 Dale Li over 4 years ago

TI__Mastermind 35520 points

Hello Ryo,

This is a minimum specification to show HOLD time from SCLK falling to previous data valid on SDO, this parameter is independent of SCLK and the sampling rate of ADC, the controller will have to read the data within this time period.

Thanks&regards,

Dale

0 Ryo Akashi over 4 years ago in reply to Dale Li

TI__Expert 8950 points

Hi Dale,

Thank you for your reply.

I understand tHT_CKDO is independent of SCLK and sampling rate.

Let me ask one question.

SDO hold time is 10nsec and Set up time is 25nsec.

It means data valid time is total 35nsec (tHT_CKDO + tSU_DOCK). Is it correct?

Thanks and best regards,

Ryo Akashi

0 Dale Li over 4 years ago in reply to Ryo Akashi

TI__Mastermind 35520 points

Hi Ryo,

Your understanding is correct.

Thanks&regards,

Dale

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ADS8664: tHT_CKDO value at fSCLK=2MHz