ADC34J42EVM: Need ADC34J42 EVM with configuration file having 50 MSPS sampling rate.

Hi Ayyappan M.,

Do you currently have the ADC34J42EVM and TSW14J56EVM and are experiencing issues capturing data, or are you wanting to have these registers pre-emptively?

The ADC34J42EVM has an onboard clocking device (LMK04828) that, by default, will provide the ADC sampling clock. In order to acheive 50 MSPS, I will need to create a config file that sets the LMK04828 dividers correctly. I will return soon with the config file.

Do you know which three analog inputs you plan to use?

Best Regards,

Dan

Hi Dan,

We are going to use Channel A,B,C.

Please provide the config file asap for the above said requirements.

Thanks,

Ayyappan M.

Hi Ayyappan M.,

After a closer look, we will not be able to use the onboard clocking solution for the ADC34J42EVM at 50 MSPS. The LMK04828's lowest VCO output is 2370 MHz, and the highest we can divide is 32 (74.0625 MHz). The most direct solution is to provide an external 100 MHz input to J10, and load the config file attached (CHD powered down).

ExternalClockJ10_Fs50MHz_FPGA100MHz_CHDpwd.cfg

The LMK04828 will pass the 100 MHz to the FPGA, and will divide by 2 for the sampling clock.

Please let me know if you have any questions.

Best Regards,

Dan

Few more questions related to this.

1) For 50 MSPS sampling rate why do we need to divide 100 MHZ by 2 and pass to FPGA (TSW14J56 EVM if I understand correctly you say as FPGA)?

Don't we need to pass to ADC34J42 EVM as it is sampling? And also for FPGA we have a HSDC PRO GUI SW to set 50 MSPS.

2) By specifications of ADC 34J42 EVM it's maximum Sampling rate is 50 MSPS according to Introduction part in page 3 in the user guide in the following link.

www.ti.com/.../slau579d.pdf

Then how it is not possible to configure to that?

3) According to your reply are you saying to do hardware manipulations in EVM? And with that along with config file loaded will it not affect other modules like JESD interface clocking and any others which is working fine already?

Please reply ASAP so that we can plan our schedule based on your inputs.

Thanks,

Ayyappan M

Hi Ayyappan M,

Did you receive the answers to the questions that were submitted through TI Customer Support? These will be very helpful in understanding how these EVMs work.

1) For 50 MSPS sampling rate why do we need to divide 100 MHZ by 2 and pass to FPGA (TSW14J56 EVM if I understand correctly you say as FPGA)?

The FPGA requires a clock that is 2X that of the sampling rate. This is how the firmware/hardware is designed for the TSW14J56EVM and the ADC34J42EVM. We use the LMK04828 that is on the ADC34J42EVM to accomplish this.

Don't we need to pass to ADC34J42 EVM as it is sampling? And also for FPGA we have a HSDC PRO GUI SW to set 50 MSPS.

Yes, the LMK04828 has multiple outputs that can have different divider settings. We are sending the ADC a 50 MHz signal for the sampling clock, and a 100MHz signal to the TSW14J56EVM, simultaneously.

2) By specifications of ADC 34J42 EVM it's maximum Sampling rate is 50 MSPS according to Introduction part in page 3 in the user guide in the following link.

www.ti.com/.../slau579d.pdf

Then how it is not possible to configure to that?

The EVM will operate at different sampling rates, but data sheet performance is not guaranteed.

3) According to your reply are you saying to do hardware manipulations in EVM? And with that along with config file loaded will it not affect other modules like JESD interface clocking and any others which is working fine already?

The solution that I am proposing does not require any hardware modifcations to either the ADC34J42EVM or TSW14J56EVM. You will need to provide an external 100 MHz signal to J10 on the ADC34J42EVM, and then load the configuration file that I shared earlier using the ADC3000 GUI. I have verified that this works on my EVMs in my lab, so JESD and everything else is fine.

Best Regards,

Dan

Hi Dan,

For replies marked in bold underlined to the following queries below I still have doubts.

2) By specifications of ADC 34J42 EVM it's maximum Sampling rate is 50 MSPS according to Introduction part in page 3 in the user guide in the following link.

www.ti.com/.../slau579d.pdf

Then how it is not possible to configure to that?

The EVM will operate at different sampling rates, but data sheet performance is not guaranteed.

Does the solution you are providing now will it not provide datasheet performance guaranteed?

3) According to your reply are you saying to do hardware manipulations in EVM? And with that along with config file loaded will it not affect other modules like JESD interface clocking and any others which is working fine already?

The solution that I am proposing does not require any hardware modifcations to either the ADC34J42EVM or TSW14J56EVM. You will need to provide an external 100 MHz signal to J10 on the ADC34J42EVM, and then load the configuration file that I shared earlier using the ADC3000 GUI. I have verified that this works on my EVMs in my lab, so JESD and everything else is fine.

a) How to provide an external 100MHZ signal to J10 on the ADC34J42 EVM.?

b) And among other ADC EVMs ADC34J43/44/45 can we get configured for 50 MSPS without this routing external 100 MHz signal to J10 or whatever to it's EVM and with datasheet performance guaranteed?

b) Also can we get the Config file for 74.0625 MHz(as you said the highest divided ,in the post dated Jan 2,2020), just in case we need?

Please reply as we are getting closer to resolve this issue posted in this thread.

Thanks,

Ayyappan M.