Hello,
in our project we use the ADC3424 part in 2-wire mode sampling at 40MSPS.
We acquire data with an FPGA that performs deserialization and bitslips the data.
We use frame clock FCLK as a reference for our bitslipping procedure.
In a few cases we observed that data at the channel and FCLK gets misaligned.
FPGA is correctly aligned to FCLK but data has an error offset by 3 to 5 bit positions.
Also when this happens, error is different for each channel of the ADC.
For example: we get an error of 3 bits for channel A and 5 bits for channel B.
We observed one additional problem when using the test patterns in ADC's erroneous state.
There seems to be bit error even between two lanes of one channel - e.g: DA0 has error of 3 bits and DA1 has an error of 4 bits.
Is this an expected behavior? I think test patterns are free running and I am unsure whether the lanes in a channel are aligned in this mode.
According to timing diagram (Figure 130 in datasheet) data should be aligned to frame clock.
Only variable propagation delay mentioned in datasheet is t_PDI that applies to propagation of input clock to FCLK.
I assume that data clock DCLK and FCLK should be always aligned considering they are sourced from the same PLL.
Can you provide me more information on timing between clocks and data channels? Is it possible there is no deterministic relationship between them?
Is aligning to FCLK clock a valid option or should we consider do the alignment with test patterns instead?
We tried to reset the ADC via reset pin and software reset but that did not change anything. Only power cycling the board helps.
Thank you.
Best regards,
Jakub