Other Parts Discussed in Thread: C2000WARE
Tool/software: Code Composer Studio
Hi friends
I am using AMC1306E25 module to read the 4 voltages with a switching frequency of ~ 250kHz in drive application. As this is manchester coded can I use this code in F280049C mcu?
Would you mind advising me on using correct code adjustments?
thanks and kind regards
Tohid
/* SDFM Sensing Parameters*/
#define SDCLK_FREQ (float)(20*1000000)
#define SD_CLK_COUNT ECAPSYSCLOCK_FREQ/SDCLK_FREQ
#define PWM_CLK_IN_SDFM_OSR (int)(((float)PWMSYSCLOCK_FREQ/(float)SDCLK_FREQ)*(float)SDFM_OSR)
#define SDFM_FILTER_TYPE 2
#define SDFM_OSR 128
//TODO setupSDFM()
void setupSDFM(uint16_t HLT, uint16_t LLT, uint16_t PWM_ticks,
uint16_t PWM_ticks_in_sdfm_osr, uint16_t SD_clk_ecap_sys_ticks,
uint16_t sdfmosr)
{
// setup CAP to generate CLK for SDFM
configureECAPforSDFMClk(SD_clk_ecap_sys_ticks);
// setup PWM 11 for syncing up the SD filter windows with motor control PWMs
// configurePWMsyncforSDFM(PWM_ticks,PWM_ticks_in_sdfm_osr);
// Setup GPIO for SD
//SD Filter 1 - Data 1
GPIO_setPadConfig(GPIO_IF_SDFM_DATA, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(GPIO_IF_SDFM_DATA,GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(GPIO_IF_SDFM_DATA, GPIO_DIR_MODE_IN);
GPIO_setPinConfig(GPIO_IF_SDFM_DATA_PIN_CONFIG);
//SD Filter 1 - Clock 1
GPIO_setPadConfig(GPIO_IF_SDFM_CLOCK, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(GPIO_IF_SDFM_CLOCK,GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(GPIO_IF_SDFM_CLOCK, GPIO_DIR_MODE_IN);
GPIO_setPinConfig(GPIO_IF_SDFM_CLOCK_PIN_CONFIG);
//SD Filter 2 - Data 2
GPIO_setPadConfig(GPIO_IO_SDFM_DATA, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(GPIO_IO_SDFM_DATA,GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(GPIO_IO_SDFM_DATA, GPIO_DIR_MODE_IN);
GPIO_setPinConfig(GPIO_IO_SDFM_DATA_PIN_CONFIG);
//SD Filter 2 - Clock 2
GPIO_setPadConfig(GPIO_IO_SDFM_CLOCK, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(GPIO_IO_SDFM_CLOCK, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(GPIO_IO_SDFM_CLOCK, GPIO_DIR_MODE_IN);
GPIO_setPinConfig(GPIO_IO_SDFM_CLOCK_PIN_CONFIG);
//SD Filter 3 - Data 3
GPIO_setPadConfig(GPIO_VO_SDFM_DATA, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(GPIO_VO_SDFM_DATA,GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(GPIO_VO_SDFM_DATA, GPIO_DIR_MODE_IN);
GPIO_setPinConfig(GPIO_VO_SDFM_DATA_PIN_CONFIG);
//SD Filter 3 - Clock 3
GPIO_setPadConfig(GPIO_VO_SDFM_CLOCK, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(GPIO_VO_SDFM_CLOCK, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(GPIO_VO_SDFM_CLOCK, GPIO_DIR_MODE_IN);
GPIO_setPinConfig(GPIO_VO_SDFM_CLOCK_PIN_CONFIG);
//SD Filter 4 - Data 4 (bus voltage)
GPIO_setPadConfig(GPIO_VBUS_SDFM_DATA, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(GPIO_VBUS_SDFM_DATA,GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(GPIO_VBUS_SDFM_DATA, GPIO_DIR_MODE_IN);
GPIO_setPinConfig(GPIO_VBUS_SDFM_DATA_PIN_CONFIG);
//SD Filter 4 - Clock 4
GPIO_setPadConfig(GPIO_VBUS_SDFM_CLOCK, GPIO_PIN_TYPE_STD);
GPIO_setQualificationMode(GPIO_VBUS_SDFM_CLOCK, GPIO_QUAL_ASYNC);
GPIO_setDirectionMode(GPIO_VBUS_SDFM_CLOCK, GPIO_DIR_MODE_IN);
GPIO_setPinConfig(GPIO_VBUS_SDFM_CLOCK_PIN_CONFIG);
/*******************************************************/
/* Input Control Module */
/*******************************************************/
//Configure Input Control Mode: Modulator Clock rate = Modulator data rate
SDFM_setupModulatorClock(IF_SDFM_BASE, IF_SDFM_FILTER,
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
SDFM_setupModulatorClock(IO_SDFM_BASE, IO_SDFM_FILTER,
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
SDFM_setupModulatorClock(VO_SDFM_BASE, VO_SDFM_FILTER,
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
SDFM_setupModulatorClock(VBUS_SDFM_BASE, VBUS_SDFM_FILTER,
SDFM_MODULATOR_CLK_EQUAL_DATA_RATE);
SDFM_enableFilter(IF_SDFM_BASE, IF_SDFM_FILTER);
SDFM_enableFilter(IO_SDFM_BASE, IO_SDFM_FILTER);
SDFM_enableFilter(VO_SDFM_BASE, VO_SDFM_FILTER);
SDFM_enableFilter(VBUS_SDFM_BASE, VBUS_SDFM_FILTER);
/*******************************************************/
/* Sinc filter Module */
/*******************************************************/
//Configure Data filter modules filter type, OSR value and enable / disable data filter
// 16 bit data representation is chosen for OSR 128 using Sinc3, from the table in the TRM
// the max value represented for OSR 128 using sinc 3 is +/-2097152 i.e. 2^21
// the max value represented for OSR 64 using sinc 3 is +/-262144 i.e. 2^18
// to represent this in 16 bit format where the first bit is sign shift by 6 bits
SDFM_setFilterType(IF_SDFM_BASE, IF_SDFM_FILTER, SDFM_FILTER_SINC_3);
SDFM_setFilterType(IO_SDFM_BASE, IO_SDFM_FILTER, SDFM_FILTER_SINC_3);
SDFM_setFilterType(VO_SDFM_BASE, VO_SDFM_FILTER, SDFM_FILTER_SINC_3);
SDFM_setFilterType(VBUS_SDFM_BASE, VBUS_SDFM_FILTER, SDFM_FILTER_SINC_3);
SDFM_setOutputDataFormat(IF_SDFM_BASE, IF_SDFM_FILTER, SDFM_DATA_FORMAT_32_BIT);
SDFM_setOutputDataFormat(IO_SDFM_BASE, IO_SDFM_FILTER, SDFM_DATA_FORMAT_32_BIT);
SDFM_setOutputDataFormat(VO_SDFM_BASE, VO_SDFM_FILTER, SDFM_DATA_FORMAT_32_BIT);
SDFM_setOutputDataFormat(VBUS_SDFM_BASE, VBUS_SDFM_FILTER, SDFM_DATA_FORMAT_32_BIT);
SDFM_setFilterOverSamplingRatio(IF_SDFM_BASE, IF_SDFM_FILTER, sdfmosr-1);
SDFM_setFilterOverSamplingRatio(IO_SDFM_BASE, IO_SDFM_FILTER, sdfmosr-1);
SDFM_setFilterOverSamplingRatio(VO_SDFM_BASE, VO_SDFM_FILTER, sdfmosr-1);
SDFM_setFilterOverSamplingRatio(VBUS_SDFM_BASE, VBUS_SDFM_FILTER, sdfmosr-1);
/*******************************************************/
/* Comparator Module */
/*******************************************************/
//Comparator HLT and LLT
//Configure Comparator module's comparator filter type and comparator's OSR value, higher threshold, lower threshold
SDFM_setComparatorFilterType(IF_SDFM_BASE, IF_SDFM_FILTER,SDFM_FILTER_SINC_3);
SDFM_setCompFilterOverSamplingRatio(IF_SDFM_BASE, IF_SDFM_FILTER,31);
SDFM_setCompFilterHighThreshold(IF_SDFM_BASE, IF_SDFM_FILTER,HLT);
SDFM_setCompFilterLowThreshold(IF_SDFM_BASE, IF_SDFM_FILTER,LLT);
SDFM_setComparatorFilterType(IO_SDFM_BASE, IO_SDFM_FILTER,SDFM_FILTER_SINC_3);
SDFM_setCompFilterOverSamplingRatio(IO_SDFM_BASE, IO_SDFM_FILTER,31);
SDFM_setCompFilterHighThreshold(IO_SDFM_BASE, IO_SDFM_FILTER,HLT);
SDFM_setCompFilterLowThreshold(IO_SDFM_BASE, IO_SDFM_FILTER,LLT);
SDFM_setComparatorFilterType(VO_SDFM_BASE, VO_SDFM_FILTER,SDFM_FILTER_SINC_3);
SDFM_setCompFilterOverSamplingRatio(VO_SDFM_BASE, VO_SDFM_FILTER,31);
SDFM_setCompFilterHighThreshold(VO_SDFM_BASE, VO_SDFM_FILTER,HLT);
SDFM_setCompFilterLowThreshold(VO_SDFM_BASE, VO_SDFM_FILTER,LLT);
SDFM_setComparatorFilterType(VBUS_SDFM_BASE, VBUS_SDFM_FILTER,SDFM_FILTER_SINC_3);
SDFM_setCompFilterOverSamplingRatio(VBUS_SDFM_BASE, VBUS_SDFM_FILTER,31);
SDFM_setCompFilterHighThreshold(VBUS_SDFM_BASE, VBUS_SDFM_FILTER,HLT);
SDFM_setCompFilterLowThreshold(VBUS_SDFM_BASE, VBUS_SDFM_FILTER,LLT);
//Set PWM sync source
SDFM_setPWMSyncSource(IF_SDFM_BASE, IF_SDFM_FILTER, SDFM_SYNC_PWM1_SOCB);
SDFM_setPWMSyncSource(IO_SDFM_BASE, IO_SDFM_FILTER, SDFM_SYNC_PWM1_SOCB);
SDFM_setPWMSyncSource(VO_SDFM_BASE, VO_SDFM_FILTER, SDFM_SYNC_PWM1_SOCB);
SDFM_setPWMSyncSource(VBUS_SDFM_BASE, VBUS_SDFM_FILTER, SDFM_SYNC_PWM1_SOCB);
SDFM_setWaitForSyncClearMode(IF_SDFM_BASE, IF_SDFM_FILTER, SDFM_AUTO_CLEAR_WAIT_FOR_SYNC);
SDFM_setWaitForSyncClearMode(IO_SDFM_BASE, IO_SDFM_FILTER, SDFM_AUTO_CLEAR_WAIT_FOR_SYNC);
SDFM_setWaitForSyncClearMode(VO_SDFM_BASE, VO_SDFM_FILTER, SDFM_AUTO_CLEAR_WAIT_FOR_SYNC);
SDFM_setWaitForSyncClearMode(VBUS_SDFM_BASE, VBUS_SDFM_FILTER, SDFM_AUTO_CLEAR_WAIT_FOR_SYNC);
SDFM_enableWaitForSync(IF_SDFM_BASE, IF_SDFM_FILTER);
SDFM_enableWaitForSync(IO_SDFM_BASE, IO_SDFM_FILTER);
SDFM_enableWaitForSync(VO_SDFM_BASE, VO_SDFM_FILTER);
SDFM_enableWaitForSync(VBUS_SDFM_BASE, VBUS_SDFM_FILTER);
/* Select SOC from counter at ctr =PRD*/
EPWM_setADCTriggerSource(INV_PWM1_BASE,EPWM_SOC_B,EPWM_SOC_TBCTR_U_CMPC);
// set CMPB to issue the pulse for PWM sync appropriately
EPWM_setCounterCompareValue(INV_PWM1_BASE,EPWM_COUNTER_COMPARE_B,
(EPWM_getTimeBasePeriod(INV_PWM1_BASE) - PWM_ticks_in_sdfm_osr*1.5));
// set CMPB to issue the pulse for PWM sync appropriately
EPWM_setCounterCompareValue(INV_PWM1_BASE,EPWM_COUNTER_COMPARE_C,
(EPWM_getTimeBasePeriod(INV_PWM1_BASE) - PWM_ticks_in_sdfm_osr*1.5));
/* Generate pulse on 1st even*/
EPWM_setADCTriggerEventPrescale(INV_PWM1_BASE,EPWM_SOC_B,1);
/* Enable SOC on A group*/
EPWM_enableADCTrigger(INV_PWM1_BASE,EPWM_SOC_B);
/*******************************************************/
/* EXTERNAL RESET */
/*******************************************************/
//PWM11.CMPC, PWM11.CMPD, PWM12.CMPC and PWM12.CMPD signals cannot synchronize the filters. This option is not being used in this example.
SDFM_enableExternalReset(IF_SDFM_BASE, IF_SDFM_FILTER);
SDFM_enableExternalReset(IO_SDFM_BASE, IO_SDFM_FILTER);
SDFM_enableExternalReset(VO_SDFM_BASE, VO_SDFM_FILTER);
SDFM_enableExternalReset(VBUS_SDFM_BASE, VBUS_SDFM_FILTER);
/*******************************************************/
/* Enable interrupts */
/*******************************************************/
//Following SDFM interrupts can be enabled / disabled using this function.
// Enable / disable comparator high threshold
// Enable / disable comparator low threshold
// Enable / disable modulator clock failure
// Enable / disable filter acknowledge
SDFM_enableInterrupt(IF_SDFM_BASE, IF_SDFM_FILTER,SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT);
SDFM_enableInterrupt(IO_SDFM_BASE, IO_SDFM_FILTER,SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT);
SDFM_enableInterrupt(VO_SDFM_BASE, VO_SDFM_FILTER,SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT);
SDFM_enableInterrupt(VBUS_SDFM_BASE, VBUS_SDFM_FILTER,SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT);
SDFM_enableInterrupt(IF_SDFM_BASE, IF_SDFM_FILTER,SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT);
SDFM_enableInterrupt(IO_SDFM_BASE, IO_SDFM_FILTER,SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT);
SDFM_enableInterrupt(VO_SDFM_BASE, VO_SDFM_FILTER,SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT);
SDFM_enableInterrupt(VBUS_SDFM_BASE, VBUS_SDFM_FILTER,SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT);
// Enable master filter bit of the SDFM module 1
SDFM_enableMasterFilter(VBUS_SDFM_BASE);
SDFM_enableMasterInterrupt(VBUS_SDFM_BASE);
SDFM_enableMasterFilter(VO_SDFM_BASE);
SDFM_enableMasterInterrupt(VO_SDFM_BASE);
SDFM_enableMasterFilter(IO_SDFM_BASE);
SDFM_enableMasterInterrupt(IO_SDFM_BASE);
SDFM_enableMasterFilter(IF_SDFM_BASE);
SDFM_enableMasterInterrupt(IF_SDFM_BASE);
}
//TODO configureECAPforSDFMClk()
void configureECAPforSDFMClk(uint16_t SD_clk_ecap_sys_ticks)
{
//Use CAP as source for the SD Clock
// PWM3A -> OUTPUTXBAR3 -> GPIO4
// PWM4A -> OUTPUTXBAR4 -> GPIO6
// Select ECAP1.OUT on Mux0
XBAR_setOutputMuxConfig(XBAR_OUTPUT3, XBAR_OUT_MUX00_ECAP1_OUT);
// Enable MUX0 for ECAP1.OUT
XBAR_enableOutputMux(XBAR_OUTPUT3, XBAR_MUX00);
// Select ECAP1.OUT on Mux0
XBAR_setOutputMuxConfig(XBAR_OUTPUT4, XBAR_OUT_MUX00_ECAP1_OUT);
// Enable MUX0 for ECAP1.OUT
XBAR_enableOutputMux(XBAR_OUTPUT4, XBAR_MUX00);
GPIO_setDirectionMode(GPIO_XBAR1,GPIO_DIR_MODE_OUT);
GPIO_setQualificationMode(GPIO_XBAR1,GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_XBAR1_PIN_CONFIG);
GPIO_setDirectionMode(GPIO_XBAR2,GPIO_DIR_MODE_OUT);
GPIO_setQualificationMode(GPIO_XBAR2,GPIO_QUAL_ASYNC);
GPIO_setPinConfig(GPIO_XBAR2_PIN_CONFIG);
// Setup APWM mode on CAP1, set period and compare registers
ECAP_enableAPWMMode(SDFM_CLK_ECAP1_BASE); // Enable APWM mode
ECAP_setAPWMPeriod(SDFM_CLK_ECAP1_BASE, SD_clk_ecap_sys_ticks-1);
ECAP_setAPWMCompare(SDFM_CLK_ECAP1_BASE, SD_clk_ecap_sys_ticks>>1);
// set next duty cycle to 50%
ECAP_setAPWMShadowPeriod(SDFM_CLK_ECAP1_BASE,SD_clk_ecap_sys_ticks-1);
ECAP_setAPWMShadowCompare(SDFM_CLK_ECAP1_BASE,SD_clk_ecap_sys_ticks>>1);
ECAP_clearInterrupt(SDFM_CLK_ECAP1_BASE,0xFF);
ECAP_clearGlobalInterrupt(SDFM_CLK_ECAP1_BASE);
// Start counters
ECAP_startCounter(SDFM_CLK_ECAP1_BASE);
}
