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ADS7052: SPI Read From ADC returns FF

Part Number: ADS7052

Hello TI, 

I studied SPI communication in ads7052 ADC Converter. I try to communicate with this ADC, by reading for 24 clocks after I set the chips selelct low, but I get only FF. Is there any reason?

I use Clock Polarity Low and clock phase = 0. 

Also, I don't use a hardware chip selecte, but I use a pin instead.

Could you please advice me on this?

Thanks in advance, 


  • Hello,

    The device only needs 24 SCLK after initial power up to start offset calibration. After that you only need 18 SCLK to complete a conversion.

    would you please provide a scope shot of 2 frames probed at the digital communication pins of the device, SDO, CS, SCLK. this will help to debug visually what is happening

    Also, for debugging I suggest using a known DC input to be able to compare the output vs the expected output.

    As for the CS pin, I am not too sure if I understand what you mean by you do not use a hardware CS. The CS pin controls with the conversation cycle, it is important to have a clean signal for CS.



  • Hello, 
    Attached you will find the schematics around ADS7052IRUGR.
    Voltage +VREF_3V3_2 on AVDD is 3.300V
    Voltage +3V3_RCV_2 on AVDD is 3.295V
    Analog voltage (BUF_OUT_OP_2) varies from 0V to +2.4V (it depends to our analog input).
    Voltage on pin 1 (output of voltage follower AD8605) in respect to -GND_ISO_2 seems to be ok measured with osciloscope.
    We do not use any pull up or pull down resistors on SPI bus.
    Accurancy of measurements is not our first goal at this moment (we can improve that later).
    Currently we can't produce any waveforms. 
    Regarding the hardware pin, please ignore this, we checked it with the logic analyzer and it works as expected. 
    Can you spot anything wrong with this hardware configuration? 
    Thanks in advance,
  • Hello,

    I apologize I overlooked that clock data you shared.

    This device outputs data on the Rising edge of sclk, but note that the MSB is not launched until after a rising edge after a falling edge of SCLK. Meaning the device needs to see a falling SCLK edge first and then on the rising edges the SDO data is launched.

    On a separate note, thank you for the schematic. Is the input a DC input, or slow moving? what is the expected frequency of the input?

    Also, how fast with the ADC be sampling? what is the expected sampling rate of the ADC?

    I ask because the input driving circuit is not optimized. The capacitor is too large and the amplifier is too slow.

    The RC filter after the op amp should not be used as a low pass filter, this circuit is needed to drive and charge the input into the ADC, thus the sizing of these components is done differently. I would suggest decreasing the cap to about 330pF, and the resistor to between 25 ohm to 200 ohm.

    Also depending on the speed the circuit  is intended for, I would suggest changing the amplifier to one with about  20Hz bandwidth.

    This should support performance at max speeds

    There is online material that can help further explain where these suggestions stem from. TI has an online video series on carious topics, including how to drive a SAR ADC as part of Precision Labs