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ADS54J20EVM: ADS54J20EVM sample rate configuration concerns

Part Number: ADS54J20EVM

Dear colleague:

Our customer has below concerns:

1. Configuration file lmk_config_onboard_983p04_msps.cfg, is 983.04MSPS the sampling frequency?

2. The input signal power of AIN/BIN is required to be greater than 17dBm on UG. Is this necessary?

3. What is the ADC output data rate in HSDC pro? What does it have to do with the sampling rate? The current input frequency is 30Mhz. When I loaded the 122.88M / 245.76M / 491.52M configuration file, the fundamental wave frequency sampled by HSDC pro was consistent with the input frequency. When the 819.2M / 983.04M /1024M configuration file is loaded, the sampled fundamental wave frequencies are all wrong, and D4 is always off and D3 is always on.

4. If you want to use 1G sampling rate, do you only need to load lmk_config_onboard_1024_msps.cfg?

Best Regards,

Rock Su

  • Rock.

    1. That is correct. The number in the LMK config file name will be the ADC clock sample rate.

    2. This was a typical power used with a signal generator connected to a band pass filter. This value depends on what type of filter is used and the signal generator. The power should be set so that the fundamental power at the ADC input is -1dBFs. This is the power used for data sheet measurements.

    3. The ADC output data rate is the rate of the data coming out of the ADC. It is not the ADC sample clock rate. If decimation is used, this value will be the ADC sample clock divided by the decimation factor. If no decimation is used, both of these will be the same rate.

    4.  The board cannot generate a 1GHz clock source using the on-board VCXO. Since this VCXO is 122.88MHz, the closet you can get to 1GHz is either 1024MHz or 983.04MHz. To generate a 1GHz clock, you can either provide the board an external 1GHz clock, or change the VCXO to a 100MHz part.