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DAC3484EVM: Clocking Questions

Expert 1545 points
Part Number: DAC3484EVM


I measured the DATACLOCK frequency on the EVM and it appears that its frequency is always half of the DACCLK frequency, regardless the setting I use on the EVM or HSDC software. 

Why is not data rate and interpolation dependent? 

I also noticed that the OSTR is periodic signal in relatively low frequency (MHz range). Why is it periodic? How does its frequency being selected? 


  • Hello,

    DATACLK is DDR fashion and is proportional to input data rate before inteprolation. The frequency will be depending on the interpolation.

    The DATACLK on the EVM is dependent on the FPGA clock, which is based on the data rate. Please refer to EVM user's guide for detail on setting the right FPGA Clock for the right data rate before intperpolation.

    There is a specific section on the datasheet on OSTR calculation. Please refer to the datasheet for more detail.