DAC80508: Output Buffer Bandwidth

Benjamin,

Multiplying Bandwidth is a term typically associated with a multiplying DAC, or MDAC. These devices have a static input impedance at the reference due to the nature of the construction and orientation of the R-2R DAC ladder, which makes them ideal for these "multiplying bandwidth" applications where an AC waveform may be applied at the reference input, and the amplitude of said AC waveform controlled at the output of the DAC.

It does not necessarily reflect the bandwidth of the output buffer since there is likely a buffer included at the VREF input pin (in the case of the AD5676), along with the parasitics of the string, and the characteristics of the output buffer. Generally speaking, AOL or GBW for the output buffer are not specified for conventional buffered string DAC devices (which is the case here for both ADI and TI devices).

The nearest specifications that are typically relevant are slew rate and settling time.

All of that said, we can look into simulation data concerning the AOL and GBW of the output buffer(s), but along the way I am also curious how you  would be using this information to ensure we're really serving the correct purpose. If you're more interested in MDAC type applications as I described above, then we should probably be looking at different devices.

Hi Kevin,

Thank you for your detailed response.  I didn't take the DAC architecture into consideration, I thought it was a GBWP of the output stage which seemed odd to me (very low).  Your explanation makes much more sense.

Slew and settling were taken into consideration already.

The application is hard to describe without giving up IP, but you can think of it as a link in a chain.  You can think of the output of the chain as 64 channels of 16b 20kHz DC coupled audio.  

Each DAC channel will output 8 multiplexed channels of voltage which gets demuxed into a cap & then buffered.

As such I'm thinking I'd need an effective sample/frame rate of 320kHz.

slew and settling seem like we'd probably meet our requirements, it seems hard to totally predict those two specifications.  The requirements are not hardeither, so if we achieved 18kHz BW of the demuxed signals, that would be acceptable for the application.

Another thing:  as I need an output of 0-3.3V, and I'm using 5x of these parts, I'm thinking of using a REF6133 as an external reference for all the devices.  Let me know if you think that's acceptable (I know the specs aren't quite as good as the internal reference, but I think it should meet our needs).

Let me know if this part still seems suitable, I start layout next week!  :)

Thanks,

Ben

Hi Ben,

I assume you would be using the common reference circuit in convenience concerning power or maybe in some calibration implementation. The input current of the reference pin for the DAC is 25uA typical at 2.5V input, so I don't think you'll have any huge issues in this configuration. Do be careful concerning power-up sequences though, as nothing should exceed VDD for the DAC at any point.

Concerning DAC BW / Settling time / Slew just remember that a majority of the specifications in the datasheet are oriented towards large steps and settling to 1 LSB at the output, which may not be necessary for your particular use case. If things look good for your update rate interests on paper (even assuming these worst-case figures), you are probably good to go. Do keep in mind that these are resistor-based DACs, though, so placeholders for some filter at the output would be recommended to mitigate the effects of the "staircase" nature of resistor based DAC outputs.