Hi,
for an FPGA simulation I am trying to set up a realistic model of the external AMV7823. Objective is to help chose the optimal internal FPGA clock frequency for the required processing cycle.
I can't find any specification for the CONVERT to DAV time in the data-sheet, in external trigger mode.
Can I assume that the worst case timing CONVERT to DAV is 5 us (200 kSPS)?
Thanks,
Charles