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AMC7823: Timing Convert to DAV

Part Number: AMC7823

Hi,

for an FPGA simulation I am trying to set up a realistic model of the external AMV7823. Objective is to help chose the optimal internal FPGA clock frequency for the required processing cycle.

I can't find any specification for the CONVERT to DAV time in the data-sheet, in external trigger mode.

Can I assume that the worst case timing CONVERT to DAV is 5 us (200 kSPS)?

Thanks,

Charles

  • Hi Charles,

    The ADC samples at approximately 200ksps, but there is some digital delay in the trigger (though minor).  In addition, this 200ksps for a single channel.  If you have all the channels enabled, then you are muxing the ADC between them.  So, for example, if you have all 8 channels enabled then it will take 8 samples before DAV is asserted (~40µs).  Assuming about 10% margin in the sample rate typical accuracy, and 1µs delay (very conservative) from the then you could estimate the delay as:

    t(CONV-DAV) = 1µs + (Nchannels × 5µs × 110%)

    Thanks,

    Paul

  • Hej Paul,

    thanks for the clarification.