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DDC114: questions about DDC114's sampling rate

Marvin Feng
Intellectual 1340 points
Part Number: DDC114
Other Parts Discussed in Thread: DDC316, IVC102

Hi Team,

Our customer is using DDC114 to collect 3 channel 100pA(max.) current. Before 3k sampling rate is ok. However, they want to increase the sampling rate to >=6ksps.

From our datasheet, it seems integration time is fixed which is only related with CLK.

Just want to double confirm with you:

1) If limit the input range to range 2(~105pC),  that is to say Cf will be smaller, is it possible to have 6k+sps?

2) If the sampling rate is fixed, do you have another recommendation? Prefer not too many channels.

3) For the unit pC, can it be equivalent to pA*1s?

Thanks!

BR

Marvin

  • 0
    TI__Expert 4640 points

    Hi Marvin,

    The ~3KSPS limit is set by many different aspects, including the digital closure (synthesis of the digital at that speed). Therefore, no, lowering the input range will not help increase that speed. 6KSPS is way out of spec, so, I don't expect the device to behave even barely ok... For those speeds, the lowest number of channels you can get is either the DDC232CK (6KSPS) with 20bit/ch or the DDC316 with only 16b/ch at 50KSPS. Unfortunately any of these will easily double the price of the solution.

    Let's talk off-line where you can describe in detail the application and maybe we can find some solution but it may actually go in the other direction (less channels), like using something like the IVC102...

    Regards,

    Edu