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DAC38RF85: SRDS_CFG2 register settings

Part Number: DAC38RF85

 Hello.

In register 0x"43E" fild BUSWIDTH default value is 010. Description incomprehensible for me.

Selects the parallel interface width (16 or 20 bits).
0 : 20 bits
1: 16 bits

I use Xilinx JESD204Phy IP. This core use 8/10 bit coding, so i need set 20 bit buswidth in this register.

I find in forum explanation that 010 is 16 bits.

bit 2 - 20
bit 3 - 16
But in DAC38RFxx EVM GUI then i set 20 bit, bit 4-2 in this register sets to 010, then i set 16 bit - to 011.

I want to understand for myself exactly how set these fields.