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ADC3423EVM: sysref register enable and disable break test pattern

Miguel Glassee
Prodigy 40 points

Part Number: ADC3423EVM

I want to generate a test pattern from the ADC3423 on the EVM, which is connected to an fpga with a FMC-ADC .

I am using the ramp pattern.  Except for the apparently known issue that the ramp only increases every 4th clock cycle, there are occasional glitches.

As I read (in the forums) that I should disable the SYSREF by disabling through the register 70Ah.

If I write to this register, it seems pattern generation breaks completely, I always get out -1 (in twos complement) whether I write a '1' or a '0'  (the default) to this register.

Any suggestion, or another suggestion to get rid of the glitches ?

  • 0
    TI__Genius 12780 points

    Hi Miguel,

    Using the EVM, If I reset the ADC first (pushing button SW1) to restore default values, I follow this sequence:

    0x0A 0x44 //Set CHA/CHB ramp pattern

    0x0B 0x44 //Set CHC/CHD ramp pattern

    0x06 0x02 //Enable Test Patterns

    I then see the ramp come across in my data capture (increment on every fourth clock).

    If I do not write the register to enable the test patter (0x06 0x02), then I get what you described in your post.

    After enabling the test pattern again, if I then go to disable the SYSREF buffer, by writing

    0x70A 0x1

    I am still able to capture the same ramp pattern.

    Best Regards,

    Dan

  • 0
    Prodigy 40 points

    No, this is unrelated to what happens with me.

    When I write to register 70a, the test pattern generation is stopped.  Strange is also that even when I write a '0', which is supposed to be the default value after reset, it is still broken.

  • 0 in reply to Miguel Glassee
    TI__Genius 12780 points

    Hi Miguel,

    Are you using the ADC3xxx GUI to perform the SPI read/writes?

    Can you please probe the SPI data pin to verify that the SPI write is correct for 0x70A? I suspect that the "7" in 0x70A is not being processed correctly since the register 0x0A controls the CHA and CHB Test Patterns. After you write to 0x70A, I would also then expect that 0x0A will read back as zero. Can you please confirm this?

    Here is a quick look at how the SPI should be configured (taking into account the register 0x70A which seems to be giving trouble).

    Are you able to write to a different register (Not the SYSREF register 0x70A. Try register address 0x608 with data value 0xA0), and see if anything happens to the digital pattern output?

    Best Regards,

    Dan