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DAC38RF85: SERDES problem

Part Number: DAC38RF85

Hello. 

I'm trying to get the JESD interface to work in my custom board.

I would like to use a subclass 0, for this i set following registers

Field SYSREF_MODE in register JESD_SYSR_MODE (8.5.56) = 0
• Field DISABLE_ERR_RPT in register JESD_ERR_OUT (8.5.53) = 1
• Field MIN_LATENCY_ENA in register JESD_MATCH (8.5.50) = 1

In FPGA i not use LMFC clock, and frame clock, in ILA sequence generation.

But, sync goes low after ILA.

I clear bits in register x"151" - sync goes higth.

I set LOS field in register x"43E" to 100 - enable detection, and i see in register x"04" that in all serdes lanes signal is los - x"00FF" value in register x"04". 

This is strange, as i see that there is an 0.6V offset on each line. also ofset voltage present in the FPGA side capacitors in this lanes.

Errors present also in JESD Alarms registers 64 - 6B.

bit 3 = write_error, bit 1 = read_error   - for all lanes.

In  some lines:

bit 12 = elastic buffer overflow (bad RBD value)
bit 11 = elastic buffer match error.

I check DAC pll, and serdes pll - all is in look state.

i attached my config file.

DAC clock frequency 6000Mhz

1 IQ pair

8 lanes

6x interpolation

Format = 82121

125 MHz Ref clk

Internal reference

K = 25;

then settings loads, load the following registers:

0x124 0x0000

0x15c 0x0000

0x40a 0xf003

0x40a 0x7003

0x000 0x5863

0x124 0x0000

0x15c 0x0000

0x000 0x5860

0x004 0x0000

0x005 0x0000

0x164 0x0000

0x165 0x0000

0x166 0x0000

0x167 0x0000

0x168 0x0000

0x169 0x0000

0x16a 0x0000

0x16b 0x0000

0x16c 0x0000

0x16d 0x0000

7206.DAC_config.cfg