ADS9224R: Performance at 3MSPS

Hi Team, 

A customer of mine has some challenges with the ADS9224R. Kindly see their situation here. Direct questions are at the end of the post. 

We are using a ADS9224R dual ADC in a zero-IF receive channel for RFID. We plan to have 25 of these receive channels interfacing to an FPGA. The ADC is intended to sample at its maximum sampling rate of 3Ms/s and we don’t want to use parallellisation of the serial data output data to be able to connect all channels to the FPGA. So we are running the serial data output at 60 MHz with a bus-width of one. We are using zone 2 datatransfer and retiming for the SPI interface (the STROBE is used as clock for the SPI data towards the FPGA)

With a 231kHz signal in the receive channel the IQ output from the ADC’s looks like the next plot:

In the plot we see discontinuities we don’t expect. These discontinuities disappear if we reduce the sampling rate to 1.5Ms/s and leave the serial data-rate at 60MHz as can be seen in the next plot:

We did check all signals in the SPI interface intensively:

• No glitches in the clock and data signals
• Strobe falling edge in the stable period of the data (the eyediagram is open)
• FPGA programmed such that double clocking (glitches) would result in more than 16 databits per sample (But never seen that happening)
• Frequencies OK
• …

From this and the fact that at 1.5Ms/s and 60MHz SPI interface, the signal looks ok, we conclude the datatransfer is OK and something is going wrong in the ADC conversion process.

We checked a lot of combinations of sample rate and SPI frequencies:

• 3Ms/s                   SPI 60MHz          -> discontinuities
• 2.4Ms/s               SPI 48MHz          -> discontinuities
• 2.4Ms/s               SPI 60MHz          -> discontinuities
• 2.0Ms/s               SPI 40MHz          -> discontinuities
• 1.5Ms/s               SPI 60MHz          -> OK
• 1.5MS/s               SPI 30MHz          -> OK
• 1.0Ms/s               SPI 20MHz          -> OK

From the above we conclude the SPI data-rate doesn’t matter, but the sampling rate of the ADC does.

In the datasheet page 29 I found the following note:

This note, which we didn’t notice during the initial design, seems to suggest one needs to use at least 2 SDO’s in parallel and keep the data-transfer within 150ns, “for optimum performance”

This note might explain the problems we see, but it is not completely clear and leaves some questions unanswered.

Can you please give an answer to the following questions:

• Is it possible to run the ADS9224R at 3Ms/s and 60MHz SPI and use 1 SDO per ADC for data output?. And what could be wrong in our current setup ?
• What is meant with “For optimum performance with zone 2 transfer ….” In the note on page 29 of the datasheet?
• Why should T_D_CONVST_CS + t_read be below 150ns as is indicated by the note ? Our measurements with 1Ms/s, SPI 20MHz show a good performance, while exceeding the 150ns ?

Thanks. 

Obinna.