DAC38RF82EVM: high phasenoise of DAC38RF82/90 with internal PLL

Hello Christoph,

I have looked at the measurement briefly and have some preliminary recommendations/comments:

1. Typically, the PLL performance will improve with increased PFD frequency. The DAC38RF8x family supports up to 500MHz of PFD. Could you please increase your reference clock to the DAC PLL to 500MHz (with decreased M divider) to see if the phase noise could improve?

2. My understanding of the problem is the peaking at 60kHz or so of phase noise performance. Your far end noise actually looks better (on the blue curve) when compared to the EVM (on the yellow curve). A couple suggestions:

a. Check if there are any switching frequencies of DC/DC power supply switching around 60kHz or so. If so, see if you can improve shielding from the switching power inductor to the DAC. The most frequent coupling of the double side band noise is due to the magnetic coupling of the power inductor to the DAC PLL inductor ring within the device package

b. pay attention to any ferrite bead or power supply filters that can potentially resonate at 60kHz. . If possible, remove these filters or inject an external, high quality analog power supply to the power supply group and retest. Please note that you have to inject high quality analog power supplies. Some bench supplies are still digital control based with digital feedback, and may create some additional noise

c. check if the PLL is locked correctly. Follow these steps as guideline to ensure PLL lock

Questions:

1. The custom board that you have, how is the routing done, especially for the PLL power rails and the clock input path? Are there any potential coupling mechanism?

2. which part are you actually going to be using? 82, 83, or the 90? Different parts may have different PLL/VCO range. This may be a problem in terms making sure the PLL frequency is locked and centered

3. I saw on your custom design measurement (blue curve) has warning mentioning set att = 0dB on the E5052. Could you please double check and confirm as this may limit your noise performance measurement?

1. Typically, the PLL performance will improve with increased PFD frequency.

The DAC38RF8x family supports up to 500MHz of PFD. Could you please increase your

reference clock to the DAC PLL to 500MHz (with decreased M divider) to see if the phase noise could improve?

The 250 MHz PFD frequency is the highest frequency we are able to use in current custom design.

We’ve tested the same configuration at DAC38RF80 EVM and see DAC38 is performing well there.

2. My understanding of the problem is the peaking at 60kHz or so of phase noise performance.

Your far end noise actually looks better (on the blue curve) when compared to the EVM (on the yellow curve).

A couple suggestions:

a. Check if there are any switching frequencies of DC/DC power supply switching around 60kHz or so.

If so, see if you can improve shielding from the switching power inductor to the DAC.

The most frequent coupling of the double side band noise is due to the magnetic coupling

of the power inductor to the DAC PLL inductor ring within the device package

There are not used circuits (DC/DC or similar) which use switching frequencies around 60kHz.

b. pay attention to any ferrite bead or power supply filters that can potentially resonate at 60kHz.

If possible, remove these filters or inject an external, high quality analog power supply to the

power supply group and retest. Please note that you have to inject high quality analog power supplies.

Some bench supplies are still digital control based with digital feedback, and may create some additional noise

We exchanged the currently used ferrite bead with the EMI filter NFM31PC276B0J3 which is used on Eval. Board.

This helps to improve the 60kHz peaking and lowers the phase noise for a bit but it’s still

about 8dB higher at marker 6 (green curve in the attached document).

c. check if the PLL is locked correctly. Follow these steps as guideline to ensure PLL lock
The PLL is locked correctly.

It was "locked manually". We incremented/decremented

the VCO tune value and set it in the mid of stable area.

We also connected the SPI bus of the EVM to the DAC on our design and controlled

and configured the DAC with the TI GUI in the similar way the configuration has been done

on the EVM. So the configuration and also PLL locking seems not to be an issue.

Questions:

1. The custom board that you have, how is the routing done, especially for the

PLL power rails and the clock input path? Are there any potential coupling mechanism?
Would you mind taking a look on the layout? We do not want to post it to the forum.

If you have time to take a look on the layout we would like to send it to you

directly.

2. which part are you actually going to be using? 82, 83, or the 90?

Different parts may have different PLL/VCO range.

This may be a problem in terms making sure the PLL frequency is locked and centered

Actually we are using the 83 with external PLL.

We plan to change to 90 with internal PLL.

We performed the internal PLL tests with both 83 and 90.

3. I saw on your custom design measurement (blue curve) has warning mentioning set

att = 0dB on the E5052. Could you please double check and confirm as

this may limit your noise performance measurement?
We checked the warning it had no influence to the measurement results.

Thank you and best regards

Christoph

Test-Setups_2.pdf