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ADS1246: /DRDY PIN stays low

David Krause1
Prodigy 10 points
Part Number: ADS1246

Hi,

For testing basic functionality of the ADS1246 I created a basic setup (see attached schematic). For reading out the data I'm using an ESP32. I can successfully read and write the command registers of ADS1246. But the /DRDY PIn stays low. So I'm guessingg there is not even a conversion going on. My Programm does the following : first execute the reset command, send the sdata command, write and read back registers, transfer the synch command and poll for /DRDY to go low. Ideally the data could be read out now (after a read and 3 NOPs). But since the /DRDY Pin just stays low all the time I can invalid values. I tested two chips and they show the same behaivor.

Hope you will help me to analyze the problem.

Regards

David

  • 0
    TI__Guru 51051 points

    Hi David,

    More than likely there is a small issue in your startup routine. Are you sending SCLKs to force DRDY high?

    From section 9.5.1.4 DRDY:

    After the DRDY pin goes low, it is forced high on the first falling edge of SCLK (so that the DRDY pin can be polled for 0 instead of waiting for a falling edge). If the DRDY pin is not taken high by clocking in SCLKs after it falls low, a short high pulse for a duration of tPWH indicates new data are ready.

    One other thing I noticed is that AINN is tied to GND. This will violate the common-mode input range of the PGA.  I suggest tying AINN to mid-supply (2.5V) if you're interested in performing a single-ended measurement on AINP. Further details can be seen in section 9.3.2 Low-Noise PGA of the datasheet.