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DAC37J84EVM: Configure CPLD to receive SPI signals from Headers JP24 and JP25

Part Number: DAC37J84EVM
Other Parts Discussed in Thread: DAC37J84, LMK04828,

Hi, TI 

We are working with the DAC37J84+TSW14J10+ZC706. Following the instructions of TSW14J10 FMC-USB Interposer Card [SLAU580B] we successfully obtained a 10MHz tone on all outputs of DAC.

In our first step we used the DAC3Xj8X GUI to configure DAC37J84 and LMK04828 registers settings. But now we are developing an SPI controller to configure DAC and PLL from the FPGA (ZC706).

We notice that DAC37J84 and LMK04828 SPI signals are driven from a CPLD (See attached image) in DAC37j84 EVM. However the CPLD input signals are not routed to ZC706 in the TSW14J10, they are connected to an FTDI-USB controller.

In DAC37j84EVM there are two headers (J24 and J25) connected to CPLD that seem to be used as SPI inputs for DAC and LMK. The problem is that we don’t know how to “tell” to CPLD that SPI signals come from headers J24 and J25.

There is a jumper (JP3) in DAC37j84 EVM to select SPI input signals to CPLD (from FMC or from FTDI-USD controller), but we don’t find anything to configure the SPI inputs signals to CPLD from headers J24 and J25.

Could you give me some advice?

Best regards,