Team,
Could you please help with the below?
We would like to drive the clock from a LVCMOS signal 3.3V amplitude (min 2.6V).
Based on the ADC datasheet the minimum wing required for the clock must be between AVDDD*0.7 and AVDD*0.3 or 3.5V and 1.5V (so a swing of 2.0V).
So we plan to drive the clock from a low jitter, low voltage buffer with a dc decoupling (serie capacitor) and to polarize the clock input at ADVDD/2.
That way we insure to have a swing of at least 2.6V and a clock signal between 1.2 and 3.8V (~300mV noise margin).
Could your team confirm there is no restriction or risk to do so?
Indeed driving the clock with a TTL (5V) buffer is not convenient at all.
I have seen already the below answer that refers to the ADS1675REF where the flip-flop is powered with 5V:
https://e2e.ti.com/support/data-converters/f/73/p/689261/2539949#2539949
Thanks in advance,
A.