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ADS1675: Drive the clock with a 3.3V amplitude (LVCMOS)?

Part Number: ADS1675

Team,

Could you please help with the below?

We would like to drive the clock from a LVCMOS signal 3.3V amplitude (min 2.6V).
Based on the ADC datasheet the minimum wing required for the clock must be between AVDDD*0.7 and AVDD*0.3 or 3.5V and 1.5V (so a swing of 2.0V).
So we plan to drive the clock from a low jitter, low voltage buffer with a dc decoupling (serie capacitor) and to polarize the clock input at ADVDD/2.
That way we insure to have a swing of at least 2.6V and a clock signal between 1.2 and 3.8V (~300mV noise margin).

Could your team confirm there is no restriction or risk to do so?
Indeed driving the clock with a TTL (5V) buffer is not convenient at all.

I have seen already the below answer that refers to the ADS1675REF where the flip-flop is powered with 5V:
https://e2e.ti.com/support/data-converters/f/73/p/689261/2539949#2539949

Thanks in advance,

A.

  • Hello Anthony,

    I do not think we have used this approach, but it should work as long the min/max voltages are met and a fast rise and fall time can be achieved.  The customer will need to evaluate this approach on the bench to make sure they can get a clean clock signal.

    Here are the general guidelines.

    For best performance, the CLK duty cycle should be very close to 50%. The rise and fall times of the clock should be less than 1ns and clock amplitude should be equal to AVDD.

    The 1nS is not strictly necessary; the Evaluation board does not achieve this rise time.  However, the 'close' 50% duty cycle is important for internal settling times.

    You are correct, the Evaluation Board uses a standard gate as a translator to go from 3.3V up to 5V.  You can purchase clock oscillators that operate from 5V supplies, and then voltage translate and PLL multiply this reference clock for the rest of the system as another approach.

    Regards,
    Keith Nicholas
    Precision ADC Applications