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ADS8920B: external components variation

Iwata Etsuji
Expert 6400 points
Part Number: ADS8920B

Hello team,

- When we would run ADS8920B in 1Msps, how much variation could be acceptable, especially for sclk (e.g. 10ppm variation)?

- When we set the OFST_CAL resister to 000b in spite of the external VREF=4.5V, should it cause the offset error rather than data sheet specification, the gain error, any drift errors, ets.?

Best regards,
Iwata Etsuji

  • 0
    TI__Mastermind 41090 points

    Hello Iwata-san,

    The data rate is set by the external host MCU, and is equal to the CONVST frequency.  SCLK can range from the minimum frequency required to clock all of the data from the device, up to the maximum SCLK of 70MHz (DVDD>2.35V).

    The OFST_CAL register corrects the ADC offset.  If not set correctly, then the DC specifications can be exceeded, including the thermal drift errors.

    I need check with the design team on which specifications are directly effected and will follow-up to this thread in 1-2 days.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    TI__Mastermind 41090 points

    Hello Iwata-san,

    The OFST_CAL is used to correct the ADC offset.  This is done internally by digitally adding a correction factor, which depends on the value of the reference voltage.  If you use a 4.5V reference with the default 5V setting for OFST_CAL, then you will have additional offset error.  However, if you perform a system calibration, then this register setting can be ignored.