Sorry for delay response. this is continue question to below
My customer has had an experiment on their system. then they observed an interesting result.
Normally, single sync pulse at first is allowed to make synchronous when single sync source mode. But my customer see delay clock out sometime. If second sync pulse inputs, no delay clock out observed, looks solving this issue.
Do you know why second sync pulse make solving this issue?
In addition, I would like to confirm delay time.
The 20ns of delay time is clock of FIFO block, right?
If so, is the correct way to input data 100MHz x 16bit with I / Q multiplexing?