• State Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 1 answer
  • Subscribers 46 subscribers
  • Views 196 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS42JB69EVM: I need some info about the LMK04828 Clock Inputs in the EVM board. I need to modify the Clock Ouputs of the ship to custom values.

user6199499
Prodigy 100 points
Part Number: ADS42JB69EVM
Other Parts Discussed in Thread: LMK04828,

Hello,

I'm developing a custom FPGA board (with a Kintex 7) that communicates with the ADS42JB69EVM board and ADC using the FMC connector. I'm going to use the LMK04828 included in the board to generate all the external clocks but I'm having difficulties understanding the configuration of this chip.

Summarizing my clocks/rates are (using JESD204B Xilinx LogiCORE IP core for the FPGA):

-Line rate = 2.5 GHz

-ADC Clock / Refclck = 250MHz

-GLBLCLK = Line rate / 40 = 62.5 MHz

-Sysref = 6.25 MHz

My main question is which frequency do I have in the CLKIN0, CLKIN1 and CLKIN2 inputs (can't find this one in the schematic)?

Thanks,

Gerard

  • 0
    TI__Guru* 91947 points

    LMK_Config_External_250Msps_Clock.cfgGerard,

    Provide a 250MHz clock to SMA J6 (LMK_CLKIN) on the ADC EVM and load the attached LMK configuration file. This will use the CLKIN1 input of the LMK to generate a 250Msps clock for the ADC, a 62.5Msps clock for the FPGA, and a 6.25Msps SYSREF clock for both.

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 100 points

    Thank you Jim,

    This helps a lot.

    Do you also know the clock frequency of CLKIN0? It would be interesting to know just in case I need it at some point.

  • 0 in reply to user6199499
    TI__Guru* 91947 points

    Gerard,

    CLKIN0 is not used. The LMK is configured for clock distribution mode which only requires one clock input (CLKIN1).

    Regards,

    Jim

  • 0 in reply to jim s
    Prodigy 100 points

    Oh yes, I understand what you are saying,

    My problem is that checking the schematic there are some things that are confusing, because they don't match exactly with what you are saying. The schematic that I'm looking at is the ADS42JBX9 EVM Rev D.

    And taking a look at it I find that CLKIN0p is connected to this (Sheet 1):

    And CLKIN1p is connected to this  (Sheet 3 & 4):

    Also J6 seems to be the USB connection, the SMA that connects to the LMK seems to be J7.

    I just want to add this information just in case somebody finds this post, but thanks to your initial answers I think that I know understand how does all of this work. I guess that I can use almost the same configuration but using the CLKIN0 input and setting the input dividers to 1.

    Thanks,

    Gerard.

  • 0 in reply to user6199499
    TI__Guru* 91947 points

    4265.LMK_Config_External_250Msps_Clock.cfgGerard,

    My bad. I thought you were using one of our other ADC EVM's. For this board, you have two options:

    1. Input a 250MHz clock to J14 and remove the shunt on SJP3 from pins 2-3 to pins 1-2.

    2. Input 250MHz clock to J21 and install C74 and remove R19.

    Use the new attached LMK file for this.

    Regards,

    Jim