ADS54J60: why my spi just can read or write the register of analog bank，it can't readback the register of jesd bank.

I have already put device clk（980M）and sysref（3.828M）on ADS54J60，should I write all register before read those back？

I just tried to digital reset as you said,and then neither analog bank nor digital bank can be readback now.

Did you give the device a hard reset after power and clocks are present? You need both SYSREF and device clock to be running. If so, please send the register writes in the order you are issuing them.

Regards,

Jim 

User,

Is this a custom board? If so, is your SPI protocol following the data sheet? Send your register writes in the order you are doing them.

Jim

yes

I am using a custom board

I can read back the register of analog bank at the beginning. Dose it means I have a right spi  protocol？

but after I give a digital reset to those registers(by write 0x4004 with 68-write 0xF7 with 01-write 0x F7 with 00 then pulse reset 0x00) then I can't readback register of

both analog bank and jesd bank.

I have System and device clk on board before I write those registers. And hard reset on RESET pin.

User,

Are you following the power up sequence per section 10.1 of the data sheet? Is your hard reset active high?

Register address 0xF7 in page 0x6800 is self clearing. Do not write a 0x00 to this location.

After you make any changes to page 0x6800, the last write should be to address 0x00 to load this values. This is done by writing a "1" then "0" to bit 0.

There may be a problem with the device clock or SYSREF. Can you probe these signals at the device pins and verify they are at the correct voltage swing and common mode level?

Regards,

Jim    

power：I have tested ADC‘s power sequence，the oscilloscope shows that time delay is about 3 miniseconds between DVDD and IOVDD(IOVDD first power up)

device clk and sysref: I have probed these signal on oscillosope, the device clk is about( vcm:2.2V,vpp:640mV),the sysref clk is about( vcm:1.23V,vpp:394mV)

reset: I try to manully reset pin 48 via VIO IP CORE of VAVIDO after all clk run, but that didn't work，I cant readback the register of jesd bank.

3301.ADS54J60.cfgUser,

Configure the ADC using the settings attached. Load them in this order and then try a read.

Regards,

Jim

I found a possible cause today,the device clk is AC coupled ，and I probe the device clk input pin of ADS54J60，it‘s Vcm bias is 0V，maybe the device unable to capture signal，but why my Vcm=0V？

I gave the right voltage and power up sequence，and my Vcm Impedance to ground is about 154KΩ。

both VCM pin and the bias voltage on device clk also 0V