HI,
For the ADS7883 power-down mode, is there any way for the device to enter power-down mode other than the following:
- From the SPI interface based on: “The device enters power-down mode if CS goes high anytime after the 2nd SCLK falling edge to before the 10th SCLK falling edge.”
- Low voltage on VDD
I ask because we think the device is going into power-down unexpectedly. On power-up, we perform an initial conversion to bring the device out of the power-down state. After that, we only perform full SPI read transactions with the CS low for all 16 bit times.
Our SPI read transactions are not at a fixed period, meaning there can be milliseconds to a second between read transactions / conversions.
Thanks,
HSG