ADS4129EVM: Schematics - ADC differential clock interface

Hi,

I'm trying to use a CDCE62005 as a clock source for the ADC ADS4129 but I don't understand the differential clock interface for the ADC represented in the schematics. I copied and adapted the following image from the schematics. Doesn't the DC bias outside the clock generator interfere with it the bias provided by the clock generator? 

Assuming I'm using LVPECL could I replace this interface by:

Thank you.

Best Regards,

João Presa