AMC1304L25: AMC1304L25 Output LVDS differential voltage

Alex

No, I am measuring from the prototype. So the load for AMC1304 output LVDS output is FPGA GPIO (But this GPIO could configure termination resistance value and we selected 100ohm termination.)  I just want to make sure is it normal to see 1Vp-p voltage in output.

By the way, a customer placing the sensing resistor nearby the IPM and as the room limitation customer can't placing AMC1304 nearby the resistor.

So they have to route the differential trace from IPM to AMCdevice , what should I notice in this scenario?

Hi Gabriel,

Would this termination be differential or single-ended in the FPGA? The 100ohm load is meant to be differential and without the 100ohm load, I am not surprised by the higher pk-pk voltages. 

Hi Alex

I suppose the FPGA is with 100 differential load.

About the 100phm load mentioned in the datasheet is it be differential too?

I have found an application note that mentioned LVDS using constant current output with 4mA current.

Are AMC1204 output is constant current output structure with 4mA current?

Hi Gabriel,

I got some input from the team to assist your questions. 

Make sure that the LVDS interface is terminated to an LVDS compliant IO port. It will set the correct impedance (differential 100Ohm) as well as common-mode voltage. If you are not using an LVDS compliant IO port, a LVDS to CMOS transceiver can be used in between, alternatively, the CMOS version of the AMC1304 could be used. 

We are looking into verifying your other point. 

Alex

Thanks for your reply.

First I wondering to know are LVDS output is constant current output topology? So if the FPGA resistance is higher than 100ohm, that will lead to the voltage swing higher than what we listed in datasheet with 100ohm resistance?